公开(公告)号：US20170294513A1

公开(公告)日：2017-10-12

申请号：US15628925

申请日：2017-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20140203364A1

公开(公告)日：2014-07-24

申请号：US14155708

申请日：2014-01-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Toshiaki IWAMATSU

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78684

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract translation: 具有在包括支撑衬底的SOI衬底上形成的n沟道MISFET的半导体器件，形成在支撑衬底上的绝缘层和形成在绝缘层上的硅层具有以下结构。 在栅电极的支撑基板上设置用于阈值调整的杂质区域，使得硅层含有碳。 可以通过半导体区域以这种方式调整阈值进行阈值调整。 此外，通过设置含有碳的硅层，即使当用于阈值调节的半导体区域的杂质扩散到穿过绝缘层的硅层时，通过注入到硅层中的碳使杂质失活。 结果，可以降低晶体管特性的波动，例如MISFET的阈值电压的波动。

公开(公告)号：US20210257459A1

公开(公告)日：2021-08-19

申请号：US17224743

申请日：2021-04-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20200066757A1

公开(公告)日：2020-02-27

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180019260A1

公开(公告)日：2018-01-18

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20160118476A1

公开(公告)日：2016-04-28

申请号：US14990242

申请日：2016-01-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Toshiaki IWAMATSU

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78684

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract translation: 具有在包括支撑衬底的SOI衬底上形成的n沟道MISFET的半导体器件，形成在支撑衬底上的绝缘层和形成在绝缘层上的硅层具有以下结构。 在栅电极的支撑基板上设置用于阈值调整的杂质区域，使得硅层含有碳。 可以通过半导体区域以这种方式调整阈值进行阈值调整。 此外，通过设置含有碳的硅层，即使当用于阈值调节的半导体区域的杂质扩散到穿过绝缘层的硅层时，通过注入到硅层中的碳使杂质失活。 结果，可以降低晶体管特性的波动，例如MISFET的阈值电压的波动。

公开(公告)号：US20130187230A1

公开(公告)日：2013-07-25

申请号：US13747537

申请日：2013-01-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。