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公开(公告)号：US20210384599A1
公开(公告)日：2021-12-09
申请号：US17307261
申请日：2021-05-04
Applicant: Raytheon Company
Inventor： Zhaoyang C. Wang , Ajay Subramanian , Jason C. Soric , Matthew A. Morton
Abstract: A method includes receiving a radio frequency (RF) input signal using at least one non-reciprocal circulator. The method also includes generating an RF output signal using at least one of multiple reflective filter elements. Each reflective filter element is configured to receive an RF signal from the at least one non-reciprocal circulator and to provide a filtered RF signal to the at least one non-reciprocal circulator. The reflective filter elements include amplitude change reflectors configured to modify amplitudes of the RF signal at different frequencies. The RF output signal represents the RF input signal as modified by the at least one of the reflective filter elements.
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公开(公告)号：US20210384598A1
公开(公告)日：2021-12-09
申请号：US17307237
申请日：2021-05-04
Applicant: Raytheon Company
Inventor： Ajay Subramanian , Zhaoyang C. Wang , Jason C. Soric , Matthew A. Morton
Abstract: A method includes receiving a radio frequency (RF) input signal using at least one non-reciprocal circulator. The method also includes generating an RF output signal using at least one of one or more reflective circuit elements. Each reflective circuit element is configured to receive an RF signal from the at least one non-reciprocal circulator and to provide a modified RF signal to the at least one non-reciprocal circulator. The RF output signal represents the RF input signal as modified by the at least one of the one or more reflective circuit elements.
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公开(公告)号：US20180366803A1
公开(公告)日：2018-12-20
申请号：US15627913
申请日：2017-06-20
Applicant: Raytheon Company
Inventor： Matthew A. Morton , Gerhard Sollner
CPC classification number: H01P1/215 , H01P1/218 , H01P1/227 , H01P1/23 , H01P3/003 , H03G11/006 , H03H2/001 , H03H7/38
Abstract: A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a substrate having a magnetic material, a signal (or center) conductor disposed on the substrate and first and second ground plane conductors disposed on the substrate. The signal conductor having a first end with a first width and a second end with a second different width such that the signal conductor is provided having a taper between the first and second ends of the signal conductor. First and second ground plane conductors are spaced apart from first and second edges of signal conductor, respectively, by a distance that changes from the first end of signal conductor to the second end of signal conductor such that signal conductor, and first and second ground plane conductors form a co-planar waveguide transmission line.
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公开(公告)号：US09705513B2
公开(公告)日：2017-07-11
申请号：US14560824
申请日：2014-12-04
Applicant: RAYTHEON COMPANY
Inventor： Matthew A. Morton , Tina P. Srivastava
Abstract: A frequency source with improved phase noise. In one embodiment a phase-locked loop is used as a component of a frequency source and a signal to noise enhancer (SNE) is used to suppress phase noise produced by the phase-locked loop. The signal to noise enhancer is a nonlinear passive device that attenuates low-power signals while transmitting high power signals with little loss. The signal to noise enhancer may be fabricated as a thin film of yttrium iron garnet (YIG) epitaxially grown on a gadolinium gallium garnet (GGG) substrate, the GGG substrate being secured to a microwave transmission line from the input to the output of the signal to noise enhancer, such that the thin film of yttrium iron garnet is close to the transmission line.
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15.发明授权Frequency conversion system with improved spurious response and frequency agility 有权具有改善的杂散响应和频率敏捷性的变频系统公开(公告)号：US09548788B2
公开(公告)日：2017-01-17
申请号：US14560834
申请日：2014-12-04
Applicant: RAYTHEON COMPANY
Inventor： Matthew A. Morton , Tina P. Srivastava
Abstract: A frequency conversion system with improved performance. In one embodiment an image reject mixer is used to perform frequency conversion providing an initial degree of suppression of the image and local oscillator leakage signals, and a signal to noise enhancer (SNE) is used to further suppress the image and local oscillator signals, the signal to noise enhancer being a nonlinear passive device that attenuates low-power signals while transmitting high power signals with little loss. The signal to noise enhancer may be fabricated as a thin film of yttrium iron garnet (YIG) epitaxially grown on a gadolinium gallium garnet (GGG) substrate, the GGG substrate secured to a microwave transmission line from the input to the output of the signal to noise enhancer, such that the thin film of yttrium iron garnet is close to the transmission line.
Abstract translation: 具有改进性能的变频系统。 在一个实施例中，使用图像抑制混频器来执行频率转换，提供图像的初始抑制程度和本地振荡器泄漏信号，并且使用信噪比增强器（SNE）来进一步抑制图像和本地振荡器信号， 信噪比增强器是一种非线性无源器件，可在损耗较小的功率信号的同时衰减低功率信号。 信号噪声增强器可以制造为在钆镓石榴石（GGG）衬底上外延生长的钇铁石榴石（YIG）的薄膜，GGG衬底固定到微波传输线，从输入到信号的输出到 噪声增强器，使得钇铁石榴石的薄膜接近传输线。
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Patent Agency Ranking
公开(公告)号：US20150303962A1
公开(公告)日：2015-10-22
申请号：US14256214
申请日：2014-04-18
Applicant: Raytheon Company
Inventor： Matthew A. Morton , Jonathan P. Comeau , Anthony Kopa
IPC: H04B1/28
Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each signal channel includes: a column III-V semiconductor sampler coupled the input signal and being responsive to sampling signals; and a column IV semiconductor controllable time delay for producing the train of sampling signals in response to a train of pulses produced on the column IV semiconductor, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.
Abstract translation: 一种具有多个N个信号通道的频率转换电路，每个信号通道馈送有输入信号和一个具有周期T和占空比T / N的脉冲串。 每个信号通道包括：耦合输入信号并对采样信号作出响应的列III-V半导体采样器; 以及列IV半导体可控时间延迟，用于响应于在列IV半导体上产生的脉冲序列产生采样信号序列，所述延时根据馈送到所述第一IV半导体的时间延迟命令信号向脉冲施加时间延迟 时间延迟 采样信号中的每一个由具有周期T和占空比T / N的每个信道中的时间延迟产生，采样信号的列中的一个采样信号相对于采样信号被延迟 在另一列火车中，采样信号为时间T / N。
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公开(公告)号：US20150130564A1
公开(公告)日：2015-05-14
申请号：US14077909
申请日：2013-11-12
Applicant: Raytheon Company
Inventor： Matthew A. Morton , Francois Y. Colomb , Robert E. Leoni , Colin S. Whelan , Traugott Carl Ludwig Gerhard Soliner
CPC classification number: H01P9/02 , H01P1/2039 , H01P1/227 , H01P9/00
Abstract: A selective frequency limiter having a magnetic material and a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.
Abstract translation: 具有磁性材料和慢波结构的选择性频率限制器被设置为将通过慢波结构传播的电磁能产生的磁场磁耦合到磁性材料中。
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公开(公告)号：US11677128B2
公开(公告)日：2023-06-13
申请号：US17307237
申请日：2021-05-04
Applicant: Raytheon Company
Inventor： Ajay Subramanian , Zhaoyang C. Wang , Jason C. Soric , Matthew A. Morton
CPC classification number: H01P1/38 , H01P1/18 , H03H11/04 , H03H2011/0488
Abstract: A method includes receiving a radio frequency (RF) input signal using at least one non-reciprocal circulator. The method also includes generating an RF output signal using at least one of one or more reflective circuit elements. Each reflective circuit element is configured to receive an RF signal from the at least one non-reciprocal circulator and to provide a modified RF signal to the at least one non-reciprocal circulator. The RF output signal represents the RF input signal as modified by the at least one of the one or more reflective circuit elements.
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19.发明授权公开(公告)号：US11522525B2
公开(公告)日：2022-12-06
申请号：US16885973
申请日：2020-05-28
Applicant: RAYTHEON COMPANY
Inventor： Ajay Subramanian , Zhaoyang C. Wang , Matthew A. Morton , Jack Holloway , John Cangeme
Abstract: A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.
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20.发明申请公开(公告)号：US20210376818A1
公开(公告)日：2021-12-02
申请号：US16885973
申请日：2020-05-28
Applicant: RAYTHEON COMPANY
Inventor： Ajay Subramanian , Zhaoyang C. Wang , Matthew A. Morton , Jack Holloway , John Cangeme
IPC: H03H17/02
Abstract: A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.
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