公开(公告)号：US11522525B2

公开(公告)日：2022-12-06

申请号：US16885973

申请日：2020-05-28

Applicant: RAYTHEON COMPANY

Inventor： Ajay Subramanian ,  Zhaoyang C. Wang ,  Matthew A. Morton ,  Jack Holloway ,  John Cangeme

IPC: H03H17/02 ,  H03H11/26 ,  H03H15/00 ,  H03H17/08 ,  H03H17/00 ,  H04B1/525

Abstract: A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

公开(公告)号：US20210376818A1

公开(公告)日：2021-12-02

申请号：US16885973

申请日：2020-05-28

Applicant: RAYTHEON COMPANY

Inventor： Ajay Subramanian ,  Zhaoyang C. Wang ,  Matthew A. Morton ,  Jack Holloway ,  John Cangeme

IPC: H03H17/02

Abstract: A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.