公开(公告)号：US20220028805A1

公开(公告)日：2022-01-27

申请号：US16938316

申请日：2020-07-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Joan Rey Villarba BUOT ,  Zhijie WANG

IPC: H01L23/64 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package is described. The IC package includes a package substrate, composed of a substrate core, a first power rail on a first surface of the substrate core, and a second power rail on a second surface of the substrate core. The IC package includes a logic die supported by the second power rail on the second surface of the substrate core. The IC package includes passive devices within the substrate core. Each of the passive devices has a first terminal and a second terminal opposite the first terminal. The first terminal of each of the passive devices is directly coupled to the first power rail, and the second terminal of each of the plurality of the passive devices is directly coupled to the second power rail. The IC package includes package bumps on the second power rail on the second surface of the substrate core.

公开(公告)号：US20240321752A1

公开(公告)日：2024-09-26

申请号：US18190019

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Sang-Jae LEE ,  Zhijie WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L25/165 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15174

Abstract: A package comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device located at least partially in the substrate. The first integrated device is coupled to the first plurality of interconnects through a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects through a second plurality of solder interconnects.

公开(公告)号：US20240194545A1

公开(公告)日：2024-06-13

申请号：US18063384

申请日：2022-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Sang-Jae LEE ,  Zhijie WANG

IPC: H01L23/06 ,  H01L21/52 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/06 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/19 ,  H01L2224/24011 ,  H01L2224/244

Abstract: Disclosed are examples of die packages that incorporate metal frames with metal pockets. One or more dies may be placed within the metal pockets. Due to the structural integrity provided by the metal frame, warpage is reduced or eliminated. As a result, die packages with thin dies may be fabricated. Further, due to the electrical conductivity provided by the metal frame, the metal frame may be used as an electrical shield to protect the dies.

公开(公告)号：US20220238488A1

公开(公告)日：2022-07-28

申请号：US17161105

申请日：2021-01-28

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Aniket PATIL ,  Zhijie WANG ,  Hong Bok WE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00

Abstract: Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

公开(公告)号：US20210375736A1

公开(公告)日：2021-12-02

申请号：US17332962

申请日：2021-05-27

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG ,  Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L21/48

Abstract: Various package configurations and methods of fabricating the same are disclosed. In some aspects, a package may include a core layer and a first layer directly attached to a first side of the core layer, where a first device is embedded in the first layer. A second layer can be directly attached to a second side of the core layer opposite the first side, where a second passive device is embedded in the second layer. A first build-up layer can be directly attached to the first layer opposite the core layer, and a second build-up layer can be directly attached to the second layer opposite the core layer.

公开(公告)号：US20250096051A1

公开(公告)日：2025-03-20

申请号：US18471069

申请日：2023-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Kun FANG ,  Suhyung HWANG ,  Sang-Jae LEE ,  Rajneesh KUMAR ,  Manuel ALDRETE ,  Zhijie WANG ,  Seongho KIM

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/16

Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate includes a cavity; and an encapsulation layer located at least between the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.

公开(公告)号：US20250062246A1

公开(公告)日：2025-02-20

申请号：US18450943

申请日：2023-08-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG ,  Hong Bok WE ,  Sang-Jae LEE

IPC: H01L23/00 ,  H01L23/498

Abstract: Disclosed are devices in which a die, such as a system-on-chip (SoC) die is attached to an interposer with a mold. Unlike convention devices, the contact area for adhesion is increased by providing vertical surfaces in addition to lateral surfaces for attachment. In so doing, possibility of delamination is decreased significantly.

公开(公告)号：US20240274516A1

公开(公告)日：2024-08-15

申请号：US18168420

申请日：2023-02-13

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG ,  Hong Bok WE ,  Sang-Jae LEE

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/373

CPC classification number: H01L23/49816 ,  H01L23/293 ,  H01L23/3737

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In an aspect, an apparatus may include: an interposer including a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically couple the first metal layer and the second metal layer, and a plurality of solder resist posts disposed on a bottom surface portion of the second metal layer; a package substrate; a die electrically coupled to the package substrate; and a thermal interface material (TIM) disposed on the die, where the TIM is configured to thermally coupled the die and the bottom surface portion of the second metal layer.

公开(公告)号：US20230352390A1

公开(公告)日：2023-11-02

申请号：US17735075

申请日：2022-05-02

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Joan Rey Villarba BUOT ,  Zhijie WANG ,  Marcus HSU ,  Sang-Jae LEE ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L24/32 ,  H01L2224/32237 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L23/49822

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.

公开(公告)号：US20220223529A1

公开(公告)日：2022-07-14

申请号：US17148367

申请日：2021-01-13

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Aniket PATIL ,  Zhijie WANG ,  Hong Bok WE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.