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    Enhanced polar code constructions by strategic placement of CRC bits
    11.
    发明授权
    Enhanced polar code constructions by strategic placement of CRC bits 有权

    公开(公告)号：US10348451B2

    公开(公告)日：2019-07-09

    申请号：US15919303

    申请日：2018-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Shrinivas Kudekar ,  Thomas Richardson

    IPC: H04L1/00 ,  H03M13/00 ,  H03M13/09 ,  H03M13/13 ,  H03M13/37 ,  H03M13/39

    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

    Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code
    12.
    发明授权
    Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code 有权

    公开(公告)号：US10312939B2

    公开(公告)日：2019-06-04

    申请号：US16003047

    申请日：2018-06-07

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Richardson ,  Joseph Binamira Soriaga ,  Shrinivas Kudekar ,  Gabi Sarkis

    IPC: H03M13/00 ,  H03M13/11 ,  H04L1/00 ,  H04L5/00

    Abstract: Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.

    Efficient encoding and decoding architecture for high-rate data transfer through a parallel bus
    13.
    发明授权
    Efficient encoding and decoding architecture for high-rate data transfer through a parallel bus 有权

    公开(公告)号：US09984035B2

    公开(公告)日：2018-05-29

    申请号：US14837806

    申请日：2015-08-27

    Applicant: QUALCOMM Incorporated

    Inventor： Shrinivas Kudekar ,  Urs Niesen

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4221 ,  G06F13/4068 ,  G06F13/4204

    Abstract: System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus selects from a sequential series of data bits a plurality of data bits for transmission over a plurality of parallel bus lines. For each bus line of the plurality of parallel bus lines, the apparatus compares a state of a current data bit selected for transmission on a current bus line during a current clock cycle with one or more conditions related to the current bus line or at least one bus line adjacent to the current bus line, wherein the one or more conditions includes a state of two data bits respectively transmitted on two bus lines adjacent to the current bus line during a previous clock cycle, and determines whether to transmit the current data bit on the current bus line based on the comparison.

    RELIABLE CHANNEL ASSISTED HYBRID-ARQ
    14.
    发明申请
    RELIABLE CHANNEL ASSISTED HYBRID-ARQ 审中-公开

    公开(公告)号：US20170085354A1

    公开(公告)日：2017-03-23

    申请号：US14861604

    申请日：2015-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Shrinivas Kudekar ,  Thomas Joseph Richardson ,  Xinzhou Wu ,  Junyi Li

    IPC: H04L5/00 ,  H04L1/18

    Abstract: Methods, systems, and devices are described for wireless communication. A transmitter may receive feedback that a station failed to decode a packet sent over a first channel, and the transmitter may determine to re-send the packet or to send parity bits over the first channel or over a second channel to assist in decoding the failed packet. The first channel may be in an unlicensed radio frequency spectrum, and the second channel may be in a licensed radio frequency spectrum and may have a higher reliability level compared to the first channel. The transmitter may determine a first channel degradation level, which may be based on a signal-to-noise ratio received from the station, and may determine an amount of parity bits to send based on the degradation. The transmitter may determine the reliability level of each channel, which may be based on a channel quality indicator.

    EFFICIENT ENCODING AND DECODING ARCHITECTURE FOR HIGH-RATE DATA TRANSFER THROUGH A PARALLEL BUS
    15.
    发明申请
    EFFICIENT ENCODING AND DECODING ARCHITECTURE FOR HIGH-RATE DATA TRANSFER THROUGH A PARALLEL BUS 有权
    通过并行总线实现高速数据传输的有效编码和解码架构

    公开(公告)号：US20170060806A1

    公开(公告)日：2017-03-02

    申请号：US14837806

    申请日：2015-08-27

    Applicant: QUALCOMM Incorporated

    Inventor： Shrinivas Kudekar ,  Urs Niesen

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4221 ,  G06F13/4068 ,  G06F13/4204

    Abstract: System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus selects from a sequential series of data bits a plurality of data bits for transmission over a plurality of parallel bus lines. For each bus line of the plurality of parallel bus lines, the apparatus compares a state of a current data bit selected for transmission on a current bus line during a current clock cycle with one or more conditions related to the current bus line or at least one bus line adjacent to the current bus line, wherein the one or more conditions includes a state of two data bits respectively transmitted on two bus lines adjacent to the current bus line during a previous clock cycle, and determines whether to transmit the current data bit on the current bus line based on the comparison.

    Abstract translation: 描述了通过多线并行总线进行数据传输/接收的系统，方法和装置。 在一个示例中，该装置从连续的数据比特序列中选择多个数据比特，以便在多个并行总线上进行传输。 对于多条并行总线线路中的每条总线，该装置将当前时钟周期内当前总线上选择的用于传输的当前数据位的状态与与当前总线相关的一个或多个条件或至少一个 总线线路，其中所述一个或多个条件包括在先前时钟周期期间分别在与当前总线线路相邻的两条总线上传输的两个数据位的状态，并且确定是否将当前数据位传送到 目前公交线路基于比较。

    Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
    19.
    发明授权
    Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes 有权

    公开(公告)号：US11239860B2

    公开(公告)日：2022-02-01

    申请号：US16655850

    申请日：2019-10-17

    Applicant: QUALCOMM Incorporated

    Inventor： Shrinivas Kudekar ,  Thomas Joseph Richardson

    IPC: H03M13/11 ,  H03M13/00 ,  H03M13/03 ,  H04L1/18 ,  H04L1/00

    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

    High performance, flexible, and compact low-density parity-check (LDPC) code
    20.
    发明授权
    High performance, flexible, and compact low-density parity-check (LDPC) code 有权

    公开(公告)号：US11032026B2

    公开(公告)日：2021-06-08

    申请号：US16289113

    申请日：2019-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Joseph Richardson ,  Shrinivas Kudekar

    IPC: H04L1/00 ,  H04L1/18 ,  H03M13/03 ,  H03M13/11 ,  H03M13/00

    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

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