公开(公告)号：US20220352359A1

公开(公告)日：2022-11-03

申请号：US17244293

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Jonghae KIM ,  Je-Hsiung LAN

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/66 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00

Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

公开(公告)号：US20210376810A1

公开(公告)日：2021-12-02

申请号：US16884891

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA ,  Milind SHAH ,  Periannan CHIDAMBARAM

IPC: H03H9/05 ,  H01L41/053 ,  H01L41/047 ,  H03H9/145 ,  H01L25/04 ,  H03H9/64 ,  H01L41/23 ,  H03H3/02 ,  H03H9/02

Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

公开(公告)号：US20210327873A1

公开(公告)日：2021-10-21

申请号：US16854313

申请日：2020-04-21

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Ranadeep DUTTA ,  Jonghae KIM

IPC: H01L27/06 ,  H03F3/213 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

公开(公告)号：US20210104447A1

公开(公告)日：2021-04-08

申请号：US16592471

申请日：2019-10-03

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01L23/367 ,  H01L27/12 ,  H01L23/552 ,  H01L23/373 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56

Abstract: Active devices in an integrated circuit (IC) die package, such as in a radio frequency front end (RFFE) package can generate significant amount of heat. This problem can become acute especially as the operating frequency is high such as in 5G NR. Also, electromagnetic interference issues can arise in such packages. One or more techniques to mitigate thermal and electrical interference issues in IC die packages are presented.

公开(公告)号：US20210098600A1

公开(公告)日：2021-04-01

申请号：US16589444

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

公开(公告)号：US20200258879A1

公开(公告)日：2020-08-13

申请号：US16274129

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A multi-gate active device includes a source region coupled to source contacts and a first drain region coupled to first drain contacts. The multi-gate active device also includes a first meshed silicide stop on the first drain region. The first meshed silicide stop surrounds the first drain contacts. The multi-gate active device further includes a first gate over a first channel between the source region and the first drain region.

公开(公告)号：US20190341381A1

公开(公告)日：2019-11-07

申请号：US15970618

申请日：2018-05-03

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Matthew Michael NOWAK

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/737 ,  H01L29/93 ,  H01L29/205 ,  H01L21/8249

Abstract: A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.

公开(公告)号：US20220069797A1

公开(公告)日：2022-03-03

申请号：US17008320

申请日：2020-08-31

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H03H9/05 ,  H03H3/02 ,  H03H3/08 ,  H03H9/10 ,  H03H9/205 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H03H9/70 ,  H03H9/72

Abstract: A substrate that includes an encapsulation layer, a first acoustic resonator, a second acoustic resonator, at least one first dielectric layer, a plurality of first interconnects, at least one second dielectric layer, and a plurality of second interconnects. The first acoustic resonator is located in the encapsulation layer. The first acoustic resonator includes a first piezoelectric substrate comprising a first thickness. The second acoustic is located in the encapsulation layer. The second acoustic resonator includes a second piezoelectric substrate comprising a second thickness that is different than the first thickness. The at least one first dielectric layer is coupled to a first surface of the encapsulation layer. The plurality of first interconnects is coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer.

公开(公告)号：US20210391321A1

公开(公告)日：2021-12-16

申请号：US16899811

申请日：2020-06-12

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Je-Hsiung LAN ,  Jonghae KIM

IPC: H01L27/06 ,  H01L21/8252

Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

公开(公告)号：US20210175181A1

公开(公告)日：2021-06-10

申请号：US16706167

申请日：2019-12-06

Applicant: QUALCOMM Incorporated

Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Ranadeep DUTTA

IPC: H01L23/552 ,  H01L25/16 ,  H01L23/00

Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.