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    THREE-DIMENSIONAL (3D) CARBON NANOTUBE GATE METAL OXIDE (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETS), AND RELATED FABRICATION PROCESSES
    11.
    发明申请
    THREE-DIMENSIONAL (3D) CARBON NANOTUBE GATE METAL OXIDE (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETS), AND RELATED FABRICATION PROCESSES 审中-公开

    公开(公告)号：US20200091448A1

    公开(公告)日：2020-03-19

    申请号：US16130457

    申请日：2018-09-13

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

    IPC: H01L51/05 ,  H01L51/00 ,  H01L27/06

    Abstract: Three-dimensional (3D) carbon nanotube gate field-effect transistors (FETs), that use carbon nanotubes to form a gate, and related fabrication methods are disclosed. A carbon nanotube gate can provide for greater channel control and enlarge the effective channel width of the 3D FET, thus increasing drive strength. Carbon nanotubes have lower surface scatter and have been found to be diffusive such that resistance dominates carrier transport, thus causing higher carrier mobility. A 3D FET can be provided that includes a gate formed from carbon nanotube(s) disposed adjacent to a semiconductor channel formed from a carbon nanotube(s). A dual-gate FET can be provided employing a carbon nanotube gate(s) comprising a front and back carbon nanotube with a semiconductor channel formed therebetween.

    Variable thickness gate oxide transcap
    12.
    发明授权
    Variable thickness gate oxide transcap 有权

    公开(公告)号：US10580908B2

    公开(公告)日：2020-03-03

    申请号：US15947667

    申请日：2018-04-06

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

    IPC: H01L29/93 ,  H01L27/08 ,  H01L29/06 ,  H01G7/06 ,  H01L29/739 ,  H01L29/94

    Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

    III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods
    17.
    发明授权
    III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods 有权

    公开(公告)号：US11545404B2

    公开(公告)日：2023-01-03

    申请号：US16868147

    申请日：2020-05-06

    Applicant: QUALCOMM Incorporated

    Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

    IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

    Abstract: Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

    Integration of vertical GaN varactor with HEMT
    18.
    发明授权
    Integration of vertical GaN varactor with HEMT 有权

    公开(公告)号：US10886266B1

    公开(公告)日：2021-01-05

    申请号：US16511099

    申请日：2019-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

    IPC: H01L27/06 ,  H01L29/93 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H03F3/195 ,  H01L29/66 ,  H01L21/02

    Abstract: Aspects generally relate to a P−N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with different materials forming various layers of the varactor and HEMT. Using different material stack-up to form the varactor and HEMT allows characteristics of the varactor and HEMT to be varied for improved performance in different operating scenarios. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

    HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) FIN FIELD-EFFECT TRANSISTOR (FINFET)
    19.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) FIN FIELD-EFFECT TRANSISTOR (FINFET) 审中-公开

    公开(公告)号：US20200251582A1

    公开(公告)日：2020-08-06

    申请号：US16266267

    申请日：2019-02-04

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

    IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

    Abstract: Certain aspects of the present disclosure generally relate to a high electron mobility transistor and techniques for fabricating the same. Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate; a channel region having a fin disposed above the substrate; a first barrier layer disposed adjacent to a first side and a second side of the first fin, wherein the first side and the second side of the first fin are opposite sides, the first barrier layer forming a heterojunction with the fin; a first dielectric layer disposed adjacent to a first side and a second side of the first barrier layer, wherein the first side and the second side of the first barrier layer are opposite sides; and a first gate region disposed adjacent to the first dielectric layer.

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