公开(公告)号：US20160043304A1

公开(公告)日：2016-02-11

申请号：US14454509

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan CHEN ,  Xiaochun ZHU ,  Xia LI ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

Abstract translation: 垂直磁隧道结（pMTJ）器件包括垂直参考层，垂直参考层表面上的隧道势垒层和隧道势垒层表面上的垂直自由层。 pMTJ器件还包括在隧道势垒层上的电介质钝化层并围绕垂直自由层。 pMTJ器件还包括介电钝化层上的高磁导率材料，其被配置为由垂直参考层磁化，并且向垂直自由层提供杂散场，该杂散场补偿来自垂直参考层的杂散场。

公开(公告)号：US20200091094A1

公开(公告)日：2020-03-19

申请号：US16132323

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Niranjan Sunil MUDAKATTE ,  Wei-Chuan CHEN ,  Paragkumar Ajaybhai THADESAR ,  Christopher POLLOCK ,  Xiaoju YU ,  Rongguo ZHOU ,  Kai LIU ,  Jonghae KIM

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/15 ,  H03H9/54 ,  H03H9/64 ,  H03H7/01 ,  H03H3/02 ,  H03H3/08

Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.

公开(公告)号：US20190132942A1

公开(公告)日：2019-05-02

申请号：US15798071

申请日：2017-10-30

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Jonghae KIM ,  Xiaoju YU ,  Mario Francisco VELEZ ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Matthew Michael NOWAK ,  Christian HOFFMANN ,  Rodrigo PACHER FERNANDES ,  Manuel HOFER ,  Peter BAINSCHAB ,  Edgar SCHMIDHAMMER ,  Stefan Leopold HATZL

IPC: H05K1/02 ,  H03H9/02 ,  H05K3/32

CPC classification number: H05K1/0233 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02086 ,  H03H9/0547 ,  H03H9/1014 ,  H03H9/1071 ,  H05K3/32

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.

公开(公告)号：US20160020250A1

公开(公告)日：2016-01-21

申请号：US14334554

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Wei-Chuan CHEN ,  Yu LU ,  Kangho LEE ,  Seung Hyuk KANG

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/224 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/73 ,  H01L27/228 ,  H01L43/08

Abstract: An MRAM cell may include a magnetic tunneling junction (MTJ). The MTJ includes a pin layer, a barrier layer, a free layer, and a capping layer. The MRAM cell further includes a bidirectional diode selector, directly coupled to an electrode of the MTJ, to enable access to the MTJ.

Abstract translation: MRAM单元可以包括磁隧道结（MTJ）。 MTJ包括针层，阻挡层，自由层和覆盖层。 MRAM单元还包括直接耦合到MTJ的电极的双向二极管选择器，以使得能够访问MTJ。

公开(公告)号：US20150311429A1

公开(公告)日：2015-10-29

申请号：US14795799

申请日：2015-07-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kangho LEE ,  Wei-Chuan CHEN ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种用于制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：US20150287910A1

公开(公告)日：2015-10-08

申请号：US14243324

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Chando PARK ,  Wei-Chuan CHEN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

Abstract translation: 用于制造磁性隧道结（MTJ）装置的多步骤蚀刻技术包括在第一蚀刻步骤中在MTJ装置的第一电极上形成第一导电硬掩模以蚀刻第一电极。 该方法还包括在第一导电硬掩模上形成第二导电硬掩模，用于在第二蚀刻步骤期间蚀刻MTJ装置的磁性层。 间隔层共形沉积在第一导电硬掩模的侧壁上。 第二导电硬掩模沉积在第一导电硬掩模上并与第一导电硬掩模的侧壁上的间隔层对准。

公开(公告)号：US20150280112A1

公开(公告)日：2015-10-01

申请号：US14229427

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kangho LEE ,  Wei-Chuan CHEN ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.