公开(公告)号：US09450540B2

公开(公告)日：2016-09-20

申请号：US14595106

申请日：2015-01-12

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Li Sun ,  Zhi Zhu

IPC: H03F3/45 ,  H03F1/30 ,  H03G3/30 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03F1/30 ,  H03F3/45076 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/4565 ,  H03F3/45766 ,  H03F2200/447 ,  H03F2200/543 ,  H03F2203/45048 ,  H03F2203/45101 ,  H03F2203/45116 ,  H03F2203/45244 ,  H03F2203/45456 ,  H03G1/0029 ,  H03G3/3036 ,  H03K19/00384 ,  H03K19/018528

Abstract: An apparatus is provided. The apparatus includes a calibration circuit configured to generate a reference signal and at least one differential circuit each being configured to operate at a calibrated transconductance over process or condition variations based on the reference signal. The calibration circuit may be configured to generate the reference signal independent of the at least one differential circuit. A method for operating at least one differential circuit is provided. The method includes generating a reference signal and operating the at least one differential circuit at a calibrated transconductance or gain over process or condition variations based on the reference signal. The reference signal may be generated independently of the at least one differential circuit.

Abstract translation: 提供了一种装置。 该装置包括被配置为产生参考信号的校准电路和至少一个差分电路，每个差分电路被配置为基于参考信号在校准的跨导处超过过程或条件变化进行操作。 校准电路可以被配置为独立于至少一个差分电路产生参考信号。 提供了一种用于操作至少一个差分电路的方法。 该方法包括产生参考信号并且以校准的跨导或基于参考信号的过程或条件变化的增益来操作至少一个差分电路。 参考信号可以独立于至少一个差分电路产生。

公开(公告)号：US09209788B2

公开(公告)日：2015-12-08

申请号：US14228049

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Xiaohua Kong ,  Zhi Zhu ,  Jie Xu

IPC: H03K19/0175 ,  H03K3/356

Abstract: A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage.

公开(公告)号：US20150304134A1

公开(公告)日：2015-10-22

申请号：US14257848

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Madjid Hafizi ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li

IPC: H04L25/02 ,  H04L7/00

CPC classification number: H04L25/0276 ,  H03K5/12 ,  H03K19/018528 ,  H04L7/0091

Abstract: A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers.

Abstract translation: 用于在通信链路上发送串行数据的驱动器电路组合电压模式和电流模式驱动器。 驱动电路使用电压模式驱动器作为主输出驱动器。 一个或多个辅助电流模式驱动器与电压模式驱动器并联连接，以通过向输出中注入电流来调整输出信号。 电压模式驱动器提供大部分输出驱动器。 因此，输出驱动器电路可以提供与电压模式驱动器相关联的功率效率益处。 电流模式驱动器可以提供例如预加重，电平调整，偏斜补偿和输出信号的其它修改。 因此，驱动器电路还可以提供与当前模式驱动器相关联的信号调节能力。

公开(公告)号：US11206012B2

公开(公告)日：2021-12-21

申请号：US17101685

申请日：2020-11-23

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Yu Song ,  Jie Xu

IPC: H03K3/012 ,  G11C11/4093 ,  H03K17/687 ,  H03F3/45

Abstract: A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

公开(公告)号：US10972108B1

公开(公告)日：2021-04-06

申请号：US16864652

申请日：2020-05-01

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Li Sun ,  Hao Liu

IPC: H03L7/081 ,  H03L7/093 ,  G06F15/78 ,  H03L7/097 ,  H03M9/00 ,  H03L7/099

Abstract: A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.

公开(公告)号：US20180219704A1

公开(公告)日：2018-08-02

申请号：US15422050

申请日：2017-02-01

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

IPC: H04L25/03 ,  H04L12/26

CPC classification number: H04L25/03273 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337 ,  H04L43/16 ,  H04L2027/0069

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：US09438188B2

公开(公告)日：2016-09-06

申请号：US14486885

申请日：2014-09-15

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Li Sun ,  Zhi Zhu

IPC: H04L25/06 ,  H03F3/45 ,  H03F3/183 ,  H04B1/16 ,  H04L25/02

CPC classification number: H03F3/45071 ,  H03F3/183 ,  H03F3/45179 ,  H03F3/45677 ,  H03F3/45713 ,  H03F2200/129 ,  H03F2200/255 ,  H03F2200/36 ,  H03F2200/453 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45112 ,  H03F2203/45302 ,  H03F2203/45306 ,  H03F2203/45418 ,  H03F2203/45422 ,  H03F2203/45424 ,  H04B1/16 ,  H04L25/0272

Abstract: In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage.

Abstract translation: 在一个实施例中，接收机包括具有差分输入和差分输出的差分共栅放大器，其中差分输入包括第一输入和第二输入，并且差分共栅放大器被配置为放大输入差分信号 在差分输入处的差分输出处的放大的差分信号。 接收机还包括被配置为感测输入差分信号的共模电压的共模电压传感器，复制电路被配置为产生在第一和第二和第二至少一个处跟踪直流（DC）电压的复制电压 第二输入和比较器，被配置为将感测的共模电压与复制电压进行比较，并且基于比较来调整输入到差分公共栅放大器的第一偏置电压，其中DC电压取决于第一偏置电压 。

公开(公告)号：US09246477B2

公开(公告)日：2016-01-26

申请号：US14228049

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Xiaohua Kong ,  Zhi Zhu ,  Jie Xu

IPC: H03K19/0175 ,  H03K3/356

CPC classification number: H03K3/35613 ,  H03F3/45475 ,  H03F2200/291 ,  H03F2203/45081 ,  H03F2203/45084

Abstract: A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage.

Abstract translation: 一种共模电压电平移位电路，包括：被配置为接收具有第一共模电压的差分信号的输入节点，耦合在输入节点之间的一对并联电容器和相应的一对输出节点，包括输出端的阈值电压电路 节点，其通过并联电容器耦合到差分信号，阈值电压电路被配置为为输出节点处的差分信号提供第二共模电压，以及根据第一共模电压的电平来控制的电流源， 电流源耦合到输出节点以实现第二共模电压。

公开(公告)号：US09209789B1

公开(公告)日：2015-12-08

申请号：US14459168

申请日：2014-08-13

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Xiaohua Kong ,  Dong Ren

IPC: H03L5/00 ,  H03K5/02 ,  H03K19/0175

CPC classification number: H03F3/505 ,  H03F1/0272 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/45708 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45292 ,  H03F2203/45416 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45594 ,  H03F2203/45604 ,  H03F2203/45664 ,  H03F2203/45702 ,  H04L25/0276

Abstract: Techniques for converting a signal from a small-signal format into a rail-to-rail format are described herein. In one embodiment, a receiver comprises a voltage-level shifter configured to shift a common-mode voltage of a differential signal to obtain a level-shifted differential signal, an amplifier configured to amplify the level-shifted differential signal into an amplified differential signal, and a driver stage configured to convert the amplified differential signal into a rail-to-rail signal. The receiver also comprises a common-mode feedback circuit configured to generate a feedback voltage that is proportional to an output common-mode voltage of the amplifier, and to generate a bias voltage for input to the amplifier based on a difference between the feedback voltage and a reference voltage, wherein the output common-mode voltage of the amplifier depends on the bias voltage.

Abstract translation: 这里描述了用于将信号从小信号格式转换为轨到轨格式的技术。 在一个实施例中，接收机包括：电压电平移位器，被配置为移位差分信号的共模电压以获得电平移位的差分信号;放大器，被配置为将电平移位的差分信号放大为放大的差分信号， 以及驱动器级，被配置为将放大的差分信号转换成轨到轨信号。 接收机还包括共模反馈电路，其被配置为产生与放大器的输出共模电压成比例的反馈电压，并且基于反馈电压和反馈电压之间的差产生用于输入到放大器的偏置电压 参考电压，其中放大器的输出共模电压取决于偏置电压。

公开(公告)号：US09195254B2

公开(公告)日：2015-11-24

申请号：US13725961

申请日：2012-12-21

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Madjid Hafizi ,  Xiaohua Kong

IPC: H03K3/00 ,  G05F3/26 ,  H04L25/03

CPC classification number: G05F3/262 ,  H04L25/03847

Abstract: A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

Abstract translation: 根据分配命令，分配电流被分成第一控制电流，第二控制电流和第三控制电流。 响应于第三控制电流产生第一控制电压。 产生第二控制电压作为第一控制电流的指示，并且产生第三控制电压作为第二控制电流的指示。 可选地，至少部分地基于第一控制电压，第二控制电压和第三控制电压来控制第一驱动器，第二驱动器和第三驱动器对输出的去加重贡献。