公开(公告)号：US20150109503A1

公开(公告)日：2015-04-23

申请号：US14579592

申请日：2014-12-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Mitsuyoshi MORI ,  Hirohisa OHTSUKI ,  Yoshiyuki OHMORI ,  Yoshihiro SATO ,  Ryohei MIYAGAWA

IPC: H04N5/378

CPC classification number: H04N5/378 ,  H01L27/14603 ,  H01L27/1461 ,  H01L27/1464 ,  H01L27/14645 ,  H04N5/3745

Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.

Abstract translation: 根据本公开的固态成像装置包括二维布置的像素，每个像素包括：金属电极; 在所述金属电极上并将光转换为电信号的光电转换层; 光电转换层上的透明电极; 电荷蓄积区域，其电连接到所述金属电极并积聚来自所述光电转换层的电荷; 放大器晶体管，其根据电荷积累区域中的电荷量施加信号电压; 以及复位晶体管，其复位电荷累积区域的电位，其中复位晶体管包括比放大器晶体管的栅极氧化物膜厚的栅极氧化膜。

公开(公告)号：US20200152690A1

公开(公告)日：2020-05-14

申请号：US16744010

申请日：2020-01-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke SAKATA ,  Mitsuyoshi MORI ,  Yutaka HIROSE ,  Hiroshi MASUDA ,  Hitoshi KURIYAMA ,  Ryohei MIYAGAWA

IPC: H01L27/148 ,  H01L27/146

Abstract: An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.

公开(公告)号：US20180114811A1

公开(公告)日：2018-04-26

申请号：US15850645

申请日：2017-12-21

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yoshihiro SATO ,  Ryohei MIYAGAWA ,  Tokuhiko TAMAKI ,  Junji HIRASE ,  Yoshiyuki OHMORI ,  Yoshiyuki MATSUNAGA

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/363 ,  H01L21/266 ,  H01L21/8234

CPC classification number: H01L27/14643 ,  H01L21/266 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14665 ,  H01L27/14689 ,  H04N5/363 ,  H04N5/378

Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

公开(公告)号：US20170221944A1

公开(公告)日：2017-08-03

申请号：US15487941

申请日：2017-04-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tokuhiko TAMAKI ,  Hirohisa OHTSUKI ,  Ryohei MIYAGAWA ,  Motonori ISHII

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14643 ,  H04N5/3698 ,  H04N5/3745

Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

公开(公告)号：US20150123180A1

公开(公告)日：2015-05-07

申请号：US14556093

申请日：2014-11-28

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yoshihiro SATO ,  Ryohei MIYAGAWA ,  Tokuhiko TAMAKI ,  Junji HIRASE ,  Yoshiyuki OHMORI ,  Yoshiyuki MATSUNAGA

IPC: H01L27/146 ,  H01L21/266 ,  H01L21/8234

CPC classification number: H01L27/14643 ,  H01L21/266 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14665 ,  H01L27/14689 ,  H04N5/363 ,  H04N5/378

Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

Abstract translation: 每个单位像素包括光电转换器，与半导体区域一起形成累积二极管的n型杂质区域，累积二极管累积由光电转换器产生的信号电荷;放大器晶体管，包括电连接到杂质区的栅电极 以及形成在放大晶体管周围并注入p型杂质的隔离区域。 放大器晶体管包括形成在栅极电极和隔离区域之间的n型源极/漏极区域和形成在栅电极下方的沟道区域。 在包括沟道区域的部分中，隔离区域中的间隙在栅极宽度方向上比在包括源极/漏极区域的部分处更宽。

公开(公告)号：US20150115339A1

公开(公告)日：2015-04-30

申请号：US14554450

申请日：2014-11-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tokuhiko TAMAKI ,  Hirohisa OHTSUKI ,  Ryohei MIYAGAWA ,  Motonori ISHII

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14643 ,  H04N5/3698 ,  H04N5/3745

Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

Abstract translation: 固态成像装置包括：以矩阵排列的像素; 为每列设置的垂直信号线，传送像素信号; 为每列设置的电源线，证明电源电压; 以及为每列提供的反馈信号线，将来自外围电路的信号传送到像素，其中每个像素包括：N型扩散层; N型扩散层上方的光电转换元件; 以及N型扩散层和光电转换元件之间的电荷累积节点，累积在光电转换元件中产生的信号电荷，反馈信号线，作为电荷累积结点的一部分的金属线，垂直信号线 并且电力线被布置在第二互连层中，并且垂直信号线和电力线设置在反馈信号线和金属线之间。