公开(公告)号：US20220181188A1

公开(公告)日：2022-06-09

申请号：US17456908

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou

IPC: H01L21/683 ,  H01L21/3065 ,  H01J37/32

Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.

公开(公告)号：US11219929B2

公开(公告)日：2022-01-11

申请号：US16896338

申请日：2020-06-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Toshiyuki Takasaki ,  Hidefumi Saeki ,  Shogo Okita

IPC: B08B3/08 ,  B08B3/04

Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.

公开(公告)号：US11189480B2

公开(公告)日：2021-11-30

申请号：US16809755

申请日：2020-03-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/78 ,  H01L21/463 ,  H01L21/82

Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.

公开(公告)号：US10297487B2

公开(公告)日：2019-05-21

申请号：US15822568

申请日：2017-11-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Noriyuki Matsubara ,  Akihiro Itou

IPC: H01L21/683 ,  H01L21/311 ,  H01L21/78 ,  H01L21/304 ,  H01L23/00 ,  H01J37/00 ,  H01L21/67

Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.

公开(公告)号：US10236266B2

公开(公告)日：2019-03-19

申请号：US15594696

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou ,  Katsumi Takano ,  Mitsuru Hiroshima

IPC: H01L21/48 ,  H01L21/67 ,  H01L21/687 ,  H01L23/498 ,  H05K13/04 ,  H01L23/00 ,  B44C1/22

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.

公开(公告)号：US12230541B2

公开(公告)日：2025-02-18

申请号：US17456914

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou ,  Toshiyuki Takasaki

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/3065

Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.

公开(公告)号：US11688641B2

公开(公告)日：2023-06-27

申请号：US16881165

申请日：2020-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi Saeki ,  Hidehiko Karasaki ,  Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/82 ,  H01L21/56 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/78

CPC classification number: H01L21/82 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/31127 ,  H01L21/568

Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.

公开(公告)号：US10276423B2

公开(公告)日：2019-04-30

申请号：US15893999

申请日：2018-02-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Koji Tamura ,  Akihiro Itou ,  Atsushi Harikai ,  Noriyuki Matsubara

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.

公开(公告)号：US10049933B2

公开(公告)日：2018-08-14

申请号：US15594690

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou ,  Katsumi Takano ,  Mitsuru Hiroshima

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L23/00 ,  H01L21/302 ,  H01L21/304

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.

公开(公告)号：US09896771B2

公开(公告)日：2018-02-20

申请号：US14606972

申请日：2015-01-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yuji Zenitani ,  Takashi Nishihara ,  Tetsuya Asano ,  Akihiro Itou ,  Hiroki Takeuchi

IPC: C25B1/02 ,  C25B9/08 ,  C25B13/04 ,  C01B3/50

CPC classification number: C25B1/02 ,  C01B3/505 ,  C25B9/08 ,  C25B13/04

Abstract: An exemplary dehydrogenation device for generating a hydrogen gas through dehydrogenation according to the present disclosure comprises an anode containing a dehydrogenation catalyst, a cathode containing catalyst capable of reducing protons, and a proton conductor disposed between the anode and the cathode. The proton conductor has a perovskite crystal structure expressed by the compositional formula AaB1-xB′xO3-δ. The A element is an alkaline-earth metal and is contained in a range of 0.4