公开(公告)号：US20130021189A1

公开(公告)日：2013-01-24

申请号：US13185059

申请日：2011-07-18

申请人： Mohammad Nizam U. Kabir ,  Brandt Braswell

发明人： Mohammad Nizam U. Kabir ,  Brandt Braswell

IPC分类号： H03M1/34 ,  H03K5/22

CPC分类号： H03K5/2481 ,  H03K5/249

摘要： A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980). In another embodiment, a comparator comprises a bias circuit (420) configured to provide a bias current; a comparator circuit (430) configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein the bias current is used to place the comparator circuit (430) in an active mode; a latch circuit (450) configured to latch the difference signal and the inverted difference signal to generate a first and second latched signals; a control circuit (470) configured to generate a control signal using at least the first and second latched signals; and a switch circuit (480) configured to use the control signal to control the bias current to place the comparator circuit (430) in an active mode and an inactive mode,

摘要翻译： 提供一个比较器。 在一个实施例中，操作比较器的方法包括提供偏置电流（920）; 比较输入信号和参考信号以确定差信号和反相差信号（930）; 锁存差分信号和反相差信号以产生第一和第二锁存信号（950）; 使用至少所述第一和第二锁存信号产生控制信号（970）; 以及响应于所述控制信号（980）控制所述偏置电流，其中响应于所述偏置电流的控制来激活和去激活所述输入信号和所述参考信号（930）。 在另一个实施例中，比较器包括被配置为提供偏置电流的偏置电路（420） 比较器电路（430），被配置为通过比较输入信号和参考信号来确定差分信号和反相差信号，其中偏置电流用于将比较器电路（430）置于有效模式; 锁存电路（450），被配置为锁存所述差分信号和所述反相差信号以产生第一和第二锁存信号; 配置为使用至少所述第一和第二锁存信号来产生控制信号的控制电路（470） 以及开关电路（480），被配置为使用所述控制信号来控制所述偏置电流以将所述比较器电路（430）置于活动模式和非活动模式，

公开(公告)号：US20080165040A1

公开(公告)日：2008-07-10

申请号：US11651858

申请日：2007-01-10

申请人： Christian J. Rotchford ,  Brandt Braswell ,  Jiangbo Gan ,  Michael L. Gomez ,  Gerald P. Miaille ,  Boris V. Razmyslovitch

发明人： Christian J. Rotchford ,  Brandt Braswell ,  Jiangbo Gan ,  Michael L. Gomez ,  Gerald P. Miaille ,  Boris V. Razmyslovitch

IPC分类号： H03M1/10

CPC分类号： H03M1/1047 ,  H03M1/66

摘要： Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

公开(公告)号：US20060279293A1

公开(公告)日：2006-12-14

申请号：US11493686

申请日：2006-07-25

申请人： Youssef Atris ,  Brandt Braswell ,  Douglas Garrity

发明人： Youssef Atris ,  Brandt Braswell ,  Douglas Garrity

IPC分类号： G01R27/26

CPC分类号： G01R19/0023 ,  G01R1/203

摘要： Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

摘要翻译： 用于感测跨过已知电阻器的电流的装置，包括开关电容器网络和具有耦合到开关电容器网络的输出的输入的放大器。 开关电容器网络被配置为对指示电流的第一和第二参考电位进行采样。 放大器被配置为基于第一和第二参考电位在放大器的输出处产生第一和第二放大电位。

公开(公告)号：US07064700B1

公开(公告)日：2006-06-20

申请号：US11154405

申请日：2005-06-15

申请人： Douglas A. Garrity ,  Brandt Braswell ,  Thierry Cassagnes ,  Christopher J. Cavanagh ,  Mohammad Nlzam U Kablr ,  David R. LoCascio

发明人： Douglas A. Garrity ,  Brandt Braswell ,  Thierry Cassagnes ,  Christopher J. Cavanagh ,  Mohammad Nlzam U Kablr ,  David R. LoCascio

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/146

摘要： A pipelined analog to digital converter (“ADC”) as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization (“DHS”) stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.

摘要翻译： 如本文所述的流水线模数转换器（“ADC”）能够处理两个或更多个输入通道。 来自多个通道的模拟输入电压使用隔离输入级同时采样（每隔一个时钟相位）。 输入级的输出通过延迟/保持和同步（“DHS”）级同时采样（每隔一个时钟相位）。 DHS级使用双重采样技术处理样品，产生残余电压采样（每个时钟相位），并以交替方式为多个通道生成数字输出。 DHS级为输入级提供相等的输入负载，增强了ADC的性能。

公开(公告)号：US20130314271A1

公开(公告)日：2013-11-28

申请号：US13480977

申请日：2012-05-25

申请人： Brandt Braswell ,  Douglas A. Garrity ,  Mohammad Nizam U. Kabir

发明人： Brandt Braswell ,  Douglas A. Garrity ,  Mohammad Nizam U. Kabir

IPC分类号： G01S13/93 ,  G01S13/00 ,  G01S13/08

CPC分类号： G01S13/34 ,  G01S7/352 ,  G01S13/931 ,  G01S2013/9314 ,  G01S2013/9321 ,  G01S2013/9325 ,  G01S2013/9332 ,  G01S2013/9342 ,  G01S2013/9346 ,  G01S2013/9375 ,  G01S2013/9378 ,  G01S2013/9385 ,  H03M3/424 ,  H03M3/448 ,  H03M3/452 ,  H03M3/454

摘要： Embodiments of vehicle-borne radar systems and methods of their operation are provided. The vehicle-borne radar system includes a transmit path and a first receive path. The transmit path is capable of producing a signal for transmission over an air interface (e.g., a frequency modulated continuous wave (FMCW) signal). The receive path includes a continuous-time (CT) sigma delta analog-to-digital converter (ADC), and the receive path is capable of receiving a reflected version of the signal from the air interface, and converting the reflected version along the receive path into a sequence of digital samples using the CT sigma delta ADC. In an embodiment, the transmit path and the receive path are integrated onto a single integrated circuit.

摘要翻译： 提供车载雷达系统的实施例及其操作方法。 车载雷达系统包括发射路径和第一接收路径。 发射路径能够产生用于通过空中接口传输的信号（例如，调频连续波（FMCW）信号）。 接收路径包括连续时间（CT）Σ-Δ模数转换器（ADC），并且接收路径能够从空中接口接收信号的反射版本，并沿接收器转换反射版本 使用CT西格玛Delta ADC的数字采样序列。 在一个实施例中，发射路径和接收路径被集成到单个集成电路上。

公开(公告)号：US08384575B1

公开(公告)日：2013-02-26

申请号：US13210021

申请日：2011-08-15

申请人： Brandt Braswell

发明人： Brandt Braswell

IPC分类号： H03M3/00

CPC分类号： H03M3/398 ,  H03M3/37 ,  H03M3/424 ,  H03M3/452 ,  H03M3/464

摘要： An analog-to-digital converter (ADC) includes a continuous time filter, a quantizer, a continuous time digital-to-analog converter, a discrete time DAC, and a switch. The quantizer has an input terminal coupled to the output terminal of the continuous time filter, and a plurality of output terminals. The continuous time DAC has a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal. The discrete time DAC has a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal. The switch has a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter.

摘要翻译： 模数转换器（ADC）包括连续时间滤波器，量化器，连续时间数模转换器，离散时间DAC和开关。 量化器具有耦合到连续时间滤波器的输出端的输入端和多个输出端。 连续时间DAC具有耦合到量化器的多个输出端子的多个输入端子和输出端子。 离散时间DAC具有耦合到量化器的多个输出端子的多个输入端子和输出端子。 开关具有耦合到连续时间DAC的输出端子的第一输入端子，耦合到离散时间DAC的输出端子的第二输入端子和耦合到连续时间滤波器的输入端子的输出端子。

公开(公告)号：US20120249237A1

公开(公告)日：2012-10-04

申请号：US13075956

申请日：2011-03-30

申请人： Douglas A. Garrity ,  Brandt Braswell

发明人： Douglas A. Garrity ,  Brandt Braswell

IPC分类号： H03G3/20

CPC分类号： H03F3/005 ,  H03F3/45475 ,  H03F3/45986 ,  H03G1/0094

摘要： Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node. The switching configuration has multiple switches that are controllable sequentially to place the gain stage circuit in a sampling state, an approximate output voltage storage state, a level shifting and gain state, and an output state.

摘要翻译： 提供了用于向输入信号施加增益的装置和方法的实施例。 开关电容器增益级电路的实施例包括输入节点，输出节点，运算放大器，相关双采样部分，相关电平转换部分和切换配置。 运算放大器具有第一放大器输入，第二放大器输入和放大器输出。 相关双采样部分包括并联布置并选择性地耦合在输入节点和中心节点之间的多个采样电容器和包括耦合到第一放大器输入的第一端子的偏移存储电容器。 相关电平移位部分包括相关电平移位电容器，其包括耦合到输出节点的第一端子。 开关配置具有可以顺序控制的多个开关，以将增益级电路置于采样状态，近似输出电压存储状态，电平移位和增益状态以及输出状态。

公开(公告)号：US07852253B2

公开(公告)日：2010-12-14

申请号：US12388231

申请日：2009-02-18

申请人： David E. Bien ,  Brandt Braswell ,  Merit Y. Hong

发明人： David E. Bien ,  Brandt Braswell ,  Merit Y. Hong

IPC分类号： H03M1/12

CPC分类号： H03M1/0604 ,  H03M1/365 ,  H03M7/165

摘要： Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.

摘要翻译： 提供了用于将模拟输入信号转换为数字输出值的装置和方法。 量化电路包括输入节点和比较器阵列，其中比较器阵列的每个比较器耦合到输入节点。 分压器布置耦合到比较器阵列并且被配置为为比较器阵列的每个比较器建立相应的阈值电压。 比较器阵列基于每个比较器的输入信号和相应的阈值电压产生数字码。 控制节点耦合到分压器装置，其中协调地配置控制节点和分压器装置以响应于控制节点处的控制信号来调整比较器阵列的至少一个比较器的阈值电压。

公开(公告)号：US07671774B2

公开(公告)日：2010-03-02

申请号：US12117357

申请日：2008-05-08

申请人： Brandt Braswell

发明人： Brandt Braswell

IPC分类号： H03M3/00

CPC分类号： H03M3/362 ,  H03M3/366 ,  H03M3/454

摘要： Apparatus and methods are provided for overload recovery in high order sigma-delta feedback topologies. An apparatus is provided for an analog-to-digital converter. The analog-to-digital converter comprises a first integrator having a first input, wherein the first integrator is configured to produce a first integrated output. A first switched resistance element is coupled between the first input and the first integrated output, wherein the first integrated output is altered when the first switched resistance element is activated. A quantizer is coupled to the first integrated output, the quantizer having a digital output wherein the quantizer converts the first integrated output to a digital value. A digital-to-analog converter is coupled between the digital output and the first input, wherein the digital-to-analog converter converts the digital value to an analog value.

摘要翻译： 提供了用于高阶Σ-Δ反馈拓扑中的过载恢复的装置和方法。 提供了一种用于模数转换器的装置。 模数转换器包括具有第一输入的第一积分器，其中第一积分器被配置为产生第一积分输出。 第一开关电阻元件耦合在第一输入和第一集成输出之间，其中当第一开关电阻元件被激活时第一集成输出被改变。 量化器耦合到第一集成输出，量化器具有数字输出，其中量化器将第一积分输出转换为数字值。 数模转换器耦合在数字输出和第一输入之间，其中数模转换器将数字值转换为模拟值。

公开(公告)号：US07595666B2

公开(公告)日：2009-09-29

申请号：US12244214

申请日：2008-10-02

申请人： Brandt Braswell ,  David R. LoCascio

发明人： Brandt Braswell ,  David R. LoCascio

IPC分类号： H03K17/00

CPC分类号： G11C27/026

摘要： A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

摘要翻译： 如本文所述的双采样开关电容器架构包括具有对应于两个单独的放大器部分的两个单独输入的放大器。 放大器使用用于第一放大器部分的第一差分晶体管对，用于第二放大器部分的第二差分晶体管对，用于第一差分晶体管对的第一尾电流偏置装置，以及用于第二差分晶体管的第二尾电流偏置装置 对。 尾电流偏置装置由偏置开关结构驱动，交替地激活一个尾电流偏压装置，同时至少部分地去激活另一尾电流偏置装置。 放大器和偏置开关结构协调以消除否则将由单个放大器部分共享的公共寄生电容引起的增益误差。