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    Two stage amplifier readout circuit in pixel level hybrid bond image sensors
    11.
    发明授权
    Two stage amplifier readout circuit in pixel level hybrid bond image sensors 有权

    公开(公告)号：US10375338B2

    公开(公告)日：2019-08-06

    申请号：US15421881

    申请日：2017-02-01

    Applicant: OmniVision Technologies, Inc.

    Inventor： Zheng Yang ,  Hiroaki Ebihara ,  Chun-Ming Tang ,  Chao-Fang Tsai ,  Rui Wang ,  Tiejun Dai

    IPC: H04N5/378 ,  H04N5/369 ,  H04N5/374 ,  H01L27/146 ,  H04N5/3745

    Abstract: A hybrid bonded image sensor has a photodiode die with macrocells having at least one photodiode and a bond contact; a supporting circuitry die with multiple supercells, each supercell having at least one macrocell unit having a bond contact coupled to the bond contact of a macrocell of the photodiode die. Each macrocell unit lies within a supercell and has a reset transistor adapted to reset photodiodes of the macrocell of the photodiode die. Each supercell has at least one common source amplifier adapted to receive signal from the bond contact of a selected macrocell unit of the supercell, the common source amplifier coupled to drive a column line through a selectable source follower. In embodiments, the common source amplifiers of several supercells drive the selectable source follower through a distributed differential amplifier.

    COMPARATOR FOR DOUBLE RAMP ANALOG TO DIGITAL CONVERTER
    12.
    发明申请
    COMPARATOR FOR DOUBLE RAMP ANALOG TO DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20180324379A1

    公开(公告)日：2018-11-08

    申请号：US16035388

    申请日：2018-07-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Zheng Yang

    IPC: H04N5/378 ,  H03K5/24

    CPC classification number: H04N5/378 ,  H03K5/2481

    Abstract: A comparator includes a first stage coupled to compare a reference voltage to an image charge voltage signal. The first stage includes first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices to receive the reference voltage and the image charge voltage signal. A first auto-zero switch is between a gate of the first NMOS input transistor and a first node. The first node is between the first NMOS input transistor and the first cascode device. A second auto-zero switch is between a gate of the second NMOS input transistor and a second node. The second node is between the second cascode device and a second PMOS transistor. A voltage difference between the first and second nodes during an auto-zero period reduces an amount of kickback that occurs during an ADC period.

    METHOD AND SYSTEM FOR IMPLEMENTING H-BANDING CANCELLATION IN AN IMAGE SENSOR
    13.
    发明申请
    METHOD AND SYSTEM FOR IMPLEMENTING H-BANDING CANCELLATION IN AN IMAGE SENSOR 有权

    公开(公告)号：US20170324910A1

    公开(公告)日：2017-11-09

    申请号：US15147741

    申请日：2016-05-05

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Zheng Yang ,  Hiroaki Ebihara

    IPC: H04N5/341 ,  H04N5/374

    CPC classification number: H04N5/341 ,  H04N5/357 ,  H04N5/374 ,  H04N5/378

    Abstract: A method for implementing H-Banding cancellation in an image sensor starts with a pixel array capturing image data. Pixel array includes a plurality of pixels to generate pixel data signals, respectively. ADC circuitry acquires the pixel data signals. ADC circuitry includes a comparator circuitry. In one embodiment, comparator circuitry 310 includes a plurality of comparators. Comparators included in comparator circuitry compare the pixel data signals, respectively, to a ramp signal received from a ramp generator to generate comparator output signals. Adjacent comparators output signals may be opposite in polarity. Other embodiments are described.

    Deep N-well driven ramp buffer
    15.
    发明授权
    Deep N-well driven ramp buffer 有权

    公开(公告)号：US12302025B2

    公开(公告)日：2025-05-13

    申请号：US18167665

    申请日：2023-02-10

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Shan Chen ,  Hiroaki Ebihara ,  Rui Wang ,  Zhenfu Tian

    IPC: H04N25/78 ,  H04N25/77

    Abstract: A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.

    Adaptive correlated multiple sampling
    16.
    发明授权
    Adaptive correlated multiple sampling 有权

    公开(公告)号：US12294804B2

    公开(公告)日：2025-05-06

    申请号：US18322431

    申请日：2023-05-23

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Jiayu Guo ,  Hiroaki Ebihara ,  Liang Zuo ,  Lihang Fan ,  Satoshi Sakurai

    IPC: H04N25/78 ,  H04N25/616

    Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

    Comparator first stage clamp
    18.
    发明授权
    Comparator first stage clamp 有权

    公开(公告)号：US11381771B1

    公开(公告)日：2022-07-05

    申请号：US17127524

    申请日：2020-12-18

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu

    IPC: H04N5/369 ,  H04N5/378 ,  H03K5/24

    Abstract: A comparator includes a first stage including a first output to generate a first output signal that transitions between an upper and lower voltage level in response to a comparison of first and second inputs of the first stage. A second stage includes an input coupled to receive the first output signal from the first output of the first stage, and a second output configured to generate a second output signal in response to the first output signal. A clamp circuit includes a first node and a second node. The first node is coupled to the first output of the first stage and the second node is coupled to a supply voltage. The clamp circuit is configured to clamp a voltage difference between the first node and the second node to clamp a voltage swing of the first output signal.

    COLUMN AMPLIFIER RESET CIRCUIT WITH COMPARATOR
    19.
    发明申请
    COLUMN AMPLIFIER RESET CIRCUIT WITH COMPARATOR 有权

    公开(公告)号：US20210021774A1

    公开(公告)日：2021-01-21

    申请号：US16516097

    申请日：2019-07-18

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Zheng Yang

    IPC: H04N5/378 ,  H04N5/3745

    Abstract: A column amplifier with a comparator for use in an image sensor includes an amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An amplifier auto-zero switch is coupled between an input of the amplifier and an output of the amplifier. A feedback capacitor coupled to an input of the amplifier. An amplifier output switch coupled between the output of the amplifier and the feedback capacitor. A comparator includes a first input coupled the amplifier output switch. A comparator auto-zero switch is coupled between the first input of the comparator and an output of the comparator.

    CMOS image sensor clamping method with divided bit lines
    20.
    发明授权
    CMOS image sensor clamping method with divided bit lines 有权

    公开(公告)号：US10827143B2

    公开(公告)日：2020-11-03

    申请号：US16222827

    申请日：2018-12-17

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara

    IPC: H04N5/378 ,  H04N5/3745 ,  H01L27/146

    Abstract: An image sensor includes a pixel array including a plurality of pixels. A bit line is coupled to a column of pixels of the pixel array. The bit line is separated in to a plurality of portions coupled to the column of pixels. The portions of the bit line are electrically isolated from one another. A readout circuit is coupled to a first portion of the bit line coupled to a first portion of rows of pixels from the column of pixels to read image data from the first portion of rows of pixels from the column of pixels. The readout circuit is further coupled to a second portion of the bit line coupled to a second portion of rows of pixels from the column of pixels to read image data from the second portion of rows of pixels from the column of pixels.

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