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公开(公告)号：US20230179889A1
公开(公告)日：2023-06-08
申请号：US17540434
申请日：2021-12-02
发明人： Chao-Fang Tsai , Zheng Yang , Chun-Hsiang Chang
IPC分类号： H04N5/3745 , H03M1/46 , H03M1/56 , H04N5/378
CPC分类号： H04N5/37455 , H03M1/468 , H03M1/462 , H03M1/56 , H04N5/378
摘要： A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
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公开(公告)号：US09859312B1
公开(公告)日：2018-01-02
申请号：US15427928
申请日：2017-02-08
发明人： Rui Wang , Hiroaki Ebihara , Zheng Yang , Chun-Ming Tang , Chao-Fang Tsai , Tiejun Dai
IPC分类号： H01L27/146
CPC分类号： H01L27/14603 , H01L27/14634 , H01L27/14636 , H01L27/1464
摘要： An image sensor includes a photodiode disposed in a first semiconductor material, and the photodiode is positioned to absorb image light through the backside of the first semiconductor material. A first floating diffusion is disposed proximate to the photodiode and coupled to receive image charge from the photodiode in response to a transfer signal applied to a transfer gate disposed between the photodiode and the first floating diffusion. A second semiconductor material, including a second floating diffusion, is disposed proximate to the frontside of the first semiconductor material. A dielectric material is disposed between the first semiconductor material and the second semiconductor material, and includes a first bonding via extending from the first floating diffusion to the second floating diffusion, a second bonding via disposed laterally proximate to the first bonding via, and a third bonding via disposed laterally proximate to the first bonding via.
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公开(公告)号：US20210105422A1
公开(公告)日：2021-04-08
申请号：US16590446
申请日：2019-10-02
发明人： Chao-Fang Tsai , Zheng Yang
摘要： A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.
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公开(公告)号：US10263031B2
公开(公告)日：2019-04-16
申请号：US15421911
申请日：2017-02-01
发明人： Rui Wang , Hiroaki Ebihara , Zheng Yang , Chun-Ming Tang , Chao-Fang Tsai , Tiejun Dai
IPC分类号： H01J40/14 , H01L27/146 , H04N5/3745 , H04N5/369
摘要： A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier.
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公开(公告)号：US11659302B1
公开(公告)日：2023-05-23
申请号：US17540434
申请日：2021-12-02
发明人： Chao-Fang Tsai , Zheng Yang , Chun-Hsiang Chang
IPC分类号： H04N25/772 , H03M1/46 , H03M1/56 , H04N25/75 , H03M1/12
CPC分类号： H04N25/772 , H03M1/462 , H03M1/468 , H03M1/56 , H04N25/75
摘要： A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
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公开(公告)号：US11196949B2
公开(公告)日：2021-12-07
申请号：US16590446
申请日：2019-10-02
发明人： Chao-Fang Tsai , Zheng Yang
摘要： A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.
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公开(公告)号：US20210368116A1
公开(公告)日：2021-11-25
申请号：US16882254
申请日：2020-05-22
发明人： Chun-Hsiang Chang , Zejian Wang , Chao-Fang Tsai , Jingwei Lai
摘要： A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.
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公开(公告)号：US11632512B2
公开(公告)日：2023-04-18
申请号：US17180520
申请日：2021-02-19
发明人： Lihang Fan , Min Qu , Chao-Fang Tsai , Chun-Hsiang Chang
摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.
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公开(公告)号：US20220269482A1
公开(公告)日：2022-08-25
申请号：US17180520
申请日：2021-02-19
发明人： Lihang Fan , Min Qu , Chao-Fang Tsai , Chun-Hsiang Chang
摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.
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公开(公告)号：US11206368B2
公开(公告)日：2021-12-21
申请号：US16882254
申请日：2020-05-22
发明人： Chun-Hsiang Chang , Zejian Wang , Chao-Fang Tsai , Jingwei Lai
摘要： A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.
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