Data readout power saving techniques for shift register structure

    公开(公告)号:US11206368B2

    公开(公告)日:2021-12-21

    申请号:US16882254

    申请日:2020-05-22

    Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.

    Dual conversion gain high dynamic range image sensor readout circuit memory storage structure

    公开(公告)号:US10432879B2

    公开(公告)日:2019-10-01

    申请号:US15872741

    申请日:2018-01-16

    Abstract: A readout circuit includes a comparator coupled to receive a ramp signal an output of a dual conversion gain pixel. A single counter is coupled to the output of the comparator. The counter is coupled to write to only one of a first or a second memory circuits at a time. A first multiplexor is coupled to load either an initial value or an initial memory value from the first memory circuit into the counter. A second multiplexor is coupled to load either a low conversion gain memory value from the first memory circuit or a high conversion gain memory value from the second memory circuit into a single data transmitter, which is coupled to transmit the received memory value to a digital processor.

    DATA READOUT POWER SAVING TECHNIQUES FOR SHIFT REGISTER STRUCTURE

    公开(公告)号:US20210368116A1

    公开(公告)日:2021-11-25

    申请号:US16882254

    申请日:2020-05-22

    Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.

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