公开(公告)号：US20150200222A1

公开(公告)日：2015-07-16

申请号：US14155848

申请日：2014-01-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L27/146 ,  H01L31/02 ,  H01L31/107

CPC classification number: H01L31/02027 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L31/107

Abstract: An imaging sensor system includes a single photon avalanche diode (SPAD) imaging array including N pixels formed in a first semiconductor layer of a first wafer. Substantially an entire thickness of the first semiconductor layer of each pixel is fully depleted such that a multiplication region included in each pixel near a front side is configured to be illuminated with photons through a back side and through the substantially entire thickness of the fully depleted first semiconductor layer. Deep n type isolation regions are disposed in the first semiconductor layer between the pixels to isolate the pixels. N digital counters are formed in a second semiconductor layer of a second wafer that is bonded to the first wafer. Each of the N digital counters is coupled to the SPAD imaging array and coupled to count output pulses generated by a respective one of the pixels.

Abstract translation: 成像传感器系统包括单个光子雪崩二极管（SPAD）成像阵列，其包括形成在第一晶片的第一半导体层中的N个像素。 基本上每个像素的第一半导体层的整个厚度被完全耗尽，使得包括在前侧附近的每个像素中的乘法区被配置为被光子照射通过背面，并且通过完全耗尽的第一 半导体层。 深度n型隔离区域设置在像素之间的第一半导体层中以隔离像素。 N个数字计数器形成在第二晶片的与第一晶片接合的第二半导体层中。 N个数字计数器中的每一个耦合到SPAD成像阵列并被耦合以对由相应的一个像素产生的输出脉冲进行计数。

公开(公告)号：US11221400B2

公开(公告)日：2022-01-11

申请号：US15937608

申请日：2018-03-27

Applicant: OmniVision Technologies, Inc.

Inventor： Eric A. G. Webster ,  Olivier Bulteel

IPC: G01S7/48 ,  G01S7/4863 ,  G01S17/10 ,  G01S7/4861 ,  G01S17/894

Abstract: A photomultiplier pixel cell includes a photon detector coupled to detect an incident photon. A quenching circuit is coupled to quench an avalanche current in the photon detector. An enable circuit is coupled to the photon detector to enable and disable the photon detector in response to an enable signal. A buffer circuit is coupled to the photon detector to generate a digital output signal having a pulse width interval in response to the avalanche current triggered in the photon detector. A first one of a plurality of inputs of a digital-to-analog converter is coupled to the buffer circuit to receive a digital output signal. The digital-to-analog converter is coupled to generate an analog output signal having a magnitude that is responsive to a total number of digital output signals received concurrently within the pulse width interval at each one of the plurality of inputs of the digital-to-analog converter.

公开(公告)号：US11029397B2

公开(公告)日：2021-06-08

申请号：US15958364

申请日：2018-04-20

Applicant: OmniVision Technologies, Inc.

Inventor： Olivier Bulteel ,  Eric A. G. Webster ,  Lindsay Grant

IPC: G01S7/48 ,  G01S7/4863 ,  G01S7/4865 ,  G01S17/36 ,  G01S7/4914 ,  G01S7/497 ,  G01S17/894

Abstract: A time-of-flight (TOF) sensor includes a light source structured to emit light and a plurality of avalanche photodiodes. The TOF sensor also includes a plurality of pulse generators, where individual pulse generators are coupled to individual avalanche photodiodes in the plurality of avalanche photodiodes. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, to perform operations. Operations may include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. In response to receiving the light with the plurality of avalanche photodiodes, a plurality of pulses may be output from the individual pulse generators corresponding to the individual photodiodes that received the light. And, in response to outputting the plurality of pulses, a timing signal may be output when the plurality of pulses overlap temporally.

公开(公告)号：US10110783B2

公开(公告)日：2018-10-23

申请号：US15469812

申请日：2017-03-27

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/355 ,  H03K19/00

Abstract: Image sensors with precharge boost are disclosed herein. An example image sensor may include pixels that each include a photodiode to receive image light and produce image charge in response, a floating diffusion to receive the image charge, a transfer gate to couple the photodiode to the floating diffusion in response to a transfer control signal, a reset gate to couple a reset voltage to the floating diffusion in response to a reset control signal, and a boost capacitor coupled between the floating diffusion and a boost voltage source, wherein, during a precharge operation, the boost voltage is provided to the boost capacitor for a portion of time the transfer gate is enabled and while the reset gate is disabled.

公开(公告)号：US20180278810A1

公开(公告)日：2018-09-27

申请号：US15469812

申请日：2017-03-27

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H04N3/14 ,  H04N5/355 ,  H03K19/00

CPC classification number: H04N3/1568 ,  H03K19/0027 ,  H04N3/1506 ,  H04N3/1518 ,  H04N3/1525 ,  H04N5/3559 ,  H04N5/3597

Abstract: Image sensors with precharge boost are disclosed herein. An example image sensor may include pixels that each include a photodiode to receive image light and produce image charge in response, a floating diffusion to receive the image charge, a transfer gate to couple the photodiode to the floating diffusion in response to a transfer control signal, a reset gate to couple a reset voltage to the floating diffusion in response to a reset control signal, and a boost capacitor coupled between the floating diffusion and a boost voltage source, wherein, during a precharge operation, the boost voltage is provided to the boost capacitor for a portion of time the transfer gate is enabled and while the reset gate is disabled.

公开(公告)号：US10050168B2

公开(公告)日：2018-08-14

申请号：US15599267

申请日：2017-05-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L31/102 ,  H01L31/02 ,  H01L31/103 ,  H01L31/107 ,  H01L31/0232 ,  H01L27/146 ,  H04N5/33 ,  H04N5/369

Abstract: An imaging sensor system includes a pixel array having a plurality of pixel cells disposed in a first semiconductor layer, where each one of the plurality of pixel cells has a single photon avalanche diode (SPAD) disposed proximate to a front side of a first semiconductor layer. Each of the plurality of pixel cells includes a guard ring disposed in the first semiconductor layer in a guard ring region proximate to the SPAD, and also includes a guard ring region reflecting structure disposed in the guard ring region proximate to the guard ring and proximate to the front side of the first semiconductor layer. The imaging sensor system also includes control circuitry coupled to the pixel array to control operation of the pixel array, and readout circuitry coupled to the pixel array to readout image data from the plurality of pixel cells.

公开(公告)号：US20180097030A1

公开(公告)日：2018-04-05

申请号：US15284961

申请日：2016-10-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sohei Manabe ,  Keiji Mabuchi ,  Takayuki Goto ,  Vincent Venezia ,  Boyd Albert Fowler ,  Eric A. G. Webster

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469

Abstract: An image sensor includes a pixel array having plurality of pixel cells arranged into a plurality of rows and a plurality of columns of pixel cells in a first semiconductor die. A plurality of pixel support circuits are arranged in a second semiconductor die that is stacked and coupled together with the first semiconductor die. A plurality of interconnect lines are coupled between the first and second semiconductor dies, and each one of the plurality of pixel cells is coupled to a corresponding one of the plurality of pixel support circuits through a corresponding one plurality of interconnect lines. A plurality of shield bumps are disposed proximate to corners of the pixel cells in the pixel array and between the first and second semiconductor dies such that each one of the plurality of shield bumps is disposed between adjacent interconnect lines along a diagonal of the pixel array.

公开(公告)号：US20180019278A1

公开(公告)日：2018-01-18

申请号：US15717071

申请日：2017-09-27

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster ,  Howard E. Rhodes ,  Dominic Massetti

IPC: H01L27/146 ,  H01L31/028

CPC classification number: H01L27/14645 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14649 ,  H01L27/14652 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/028

Abstract: A method of image sensor fabrication includes forming a second semiconductor layer on a back side of a first semiconductor layer. The method also includes forming one or more groups of pixels disposed in a front side of the first semiconductor layer. The one or more groups of pixels include a first portion of pixels separated from the second semiconductor layer by a spacer region, and a second portion of pixels, where a first doped region of the second portion of pixels is in contact with the second semiconductor layer. Pinning wells are also formed and separate individual pixels in the one or more groups of pixels, and the pinning wells extend through the first semiconductor layer. Deep pinning wells are also formed and separate the one or more groups of pixels.

公开(公告)号：US09209320B1

公开(公告)日：2015-12-08

申请号：US14454460

申请日：2014-08-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L31/02 ,  H01L27/146

CPC classification number: H01L31/02027 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/107 ,  H01L31/1892 ,  Y02E10/50

Abstract: A method of fabricating an avalanche photodiode pixel includes growing a second doped semiconductor layer on a first doped semiconductor layer having a first doping concentration. The second doped semiconductor layer is grown with a second doping concentration and is of an opposite majority charge carrier type as the first doped semiconductor layer. A doped contact region having a third doping concentration is formed in the second doped semiconductor layer between the doped contact region and the first doped semiconductor layer. The doped contact region is of a same majority charge carrier type as the second doped semiconductor layer. The third doping concentration is greater than the second doping concentration. A guard ring region is formed in the second doped semiconductor layer, is of an opposite majority charge carrier type as the second doped semiconductor layer, and extends through the second doped semiconductor layer surrounding the doped contact region.

Abstract translation: 制造雪崩光电二极管像素的方法包括在具有第一掺杂浓度的第一掺杂半导体层上生长第二掺杂半导体层。 第二掺杂半导体层以第二掺杂浓度生长，并且具有与第一掺杂半导体层相反的多数电荷载流子类型。 在掺杂接触区域和第一掺杂半导体层之间的第二掺杂半导体层中形成具有第三掺杂浓度的掺杂接触区域。 掺杂接触区域具有与第二掺杂半导体层相同的多数电荷载流子类型。 第三掺杂浓度大于第二掺杂浓度。 保护环区形成在第二掺杂半导体层中，具有与第二掺杂半导体层相反的大多数电荷载流子类型，并延伸穿过包围掺杂接触区的第二掺杂半导体层。

公开(公告)号：US20150041627A1

公开(公告)日：2015-02-12

申请号：US13964987

申请日：2013-08-12

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L27/144

CPC classification number: H01L27/14634 ,  H01L27/144

Abstract: A photon detection device includes a first wafer having an array of photon detection cells partitioned into a plurality of photon detection blocks arranged in the first wafer. A second wafer having a plurality of block readout circuits arranged thereon is also included. An interconnect wafer is disposed between the first wafer and the second wafer. The interconnect wafer includes a plurality of conductors having substantially equal lengths. Each one of the plurality of conductors is coupled between a corresponding one of the plurality of photon detection blocks in the first wafer and a corresponding one of the plurality of block readout circuits such that signal propagation delays between each one of the plurality of photon detection blocks and each one of the plurality of block readout circuits are substantially equal.

Abstract translation: 光子检测装置包括具有分隔成布置在第一晶片中的多个光子检测块的光子检测单元阵列的第一晶片。 还包括其上布置有多个块读出电路的第二晶片。 互连晶片设置在第一晶片和第二晶片之间。 互连晶片包括具有基本相等长度的多个导体。 多个导体中的每一个耦合在第一晶片中的多个光子检测块中的对应一个和多个块读出电路中的相应一个之间，使得多个光子检测块中的每一个之间的信号传播延迟 并且多个块读出电路中的每一个基本相等。