公开(公告)号：US10763212B1

公开(公告)日：2020-09-01

申请号：US16388314

申请日：2019-04-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Cheng-Hsien Hsieh ,  Ching-Chia Huang ,  Chen-Lun Ting ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L23/532 ,  H01L27/108 ,  H01L23/528

Abstract: A semiconductor structure includes a substrate including a surface, a first doped region and a second doped region, wherein the first doped region and the second doped region are disposed under the surface; a gate structure disposed between the first doped region and the second doped region; a capacitor disposed over and electrically connected to the first doped region; and a bit line disposed over and electrically connected to the second doped region, wherein the bit line includes a conductive portion and an insulating portion surrounding the conductive portion, and the insulating portion includes ferroelectric material.

公开(公告)号：US10559661B2

公开(公告)日：2020-02-11

申请号：US15866888

申请日：2018-01-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

Abstract: The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.

公开(公告)号：US10381351B2

公开(公告)日：2019-08-13

申请号：US15879929

申请日：2018-01-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/76 ,  H01L27/108 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.

公开(公告)号：US11315930B2

公开(公告)日：2022-04-26

申请号：US16792157

申请日：2020-02-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Wei-Ming Liao

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/49 ,  H01L29/08 ,  H01L23/532 ,  H01L21/306

Abstract: A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.

公开(公告)号：US10937886B2

公开(公告)日：2021-03-02

申请号：US16297747

申请日：2019-03-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.

公开(公告)号：US10903080B2

公开(公告)日：2021-01-26

申请号：US16107457

申请日：2018-08-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/265

Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

公开(公告)号：US10559560B2

公开(公告)日：2020-02-11

申请号：US16229802

申请日：2018-12-21

Applicant: Nanya Technology Corporation

Inventor： Fang-Wen Liu ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L27/02 ,  H01L49/02

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

公开(公告)号：US10461191B2

公开(公告)日：2019-10-29

申请号：US16183700

申请日：2018-11-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L21/3065 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L21/762 ,  H01L27/108 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

公开(公告)号：US10446556B2

公开(公告)日：2019-10-15

申请号：US16184636

申请日：2018-11-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Ming Liao

IPC: H01L27/108 ,  G11C11/401

Abstract: The present disclosure provides a method for preparing a semiconductor memory structure. The method includes the following steps: providing a substrate comprising a plurality of active regions extending in a first direction; forming a plurality of first trenches in the substrate, the first trenches comprising a first depth and extending in a second direction different from the first direction; forming a plurality of buried digit lines in the first trenches; forming a plurality of second trenches in the substrate, the second trenches comprising a second depth and extending in a third direction different from the first direction and the second direction; deepening portions of the second trenches to form a plurality of third trenches in the substrate, the third trenches comprising a third depth; and forming a plurality of buried word lines in the third trenches.