公开(公告)号：US09419592B2

公开(公告)日：2016-08-16

申请号：US14478851

申请日：2014-09-05

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Jose de Jesus Pineda De Gyvez

IPC: H03K3/00 ,  H03K3/037 ,  H03K3/356

CPC classification number: H03K3/0372 ,  H03K3/0375 ,  H03K3/356121 ,  H03K3/356139 ,  H03K3/356156

Abstract: A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.

Abstract translation: 提供了一种顺序电路布置和方法，其中将锁存输入信号和输入信号的锁存版本进行比较以导出差分信号。 该差分信号可以在输入的变化不被传播到输出时检测。 第二逻辑门装置从差分信号的乘积和差分信号的延迟版本中导出误差信号。 这意味着电路的正常运行不会被检测为只有当锁存的输出在正常预期的延迟是创建的误差信号之后不能跟随输入时才是错误的。 根据误差信号选择锁存元件输出或锁存元件输出的反相形式。

公开(公告)号：US10565380B2

公开(公告)日：2020-02-18

申请号：US15646299

申请日：2017-07-11

Applicant: NXP B.V.

Inventor： Piotr Polak ,  Vibhu Sharma

IPC: G06F8/65 ,  H04L9/32 ,  G06F21/57 ,  G06F9/445 ,  H04L29/06 ,  H04W12/00

Abstract: An apparatus comprising an authentication processor configured to, based on received firmware and predetermined cryptographic authentication information, provide for cryptographic based authentication of the received firmware to control execution of the received firmware by any one of a plurality of processors. Each processor of the plurality of processors is uniquely addressable by a boot sequencer.

公开(公告)号：US09825918B2

公开(公告)日：2017-11-21

申请号：US14812909

申请日：2015-07-29

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Matthias Berthold Muth

IPC: G06F21/00 ,  H04L29/06 ,  G06F13/42 ,  G06F21/56 ,  H04L12/40

CPC classification number: H04L63/0428 ,  G06F13/4282 ,  G06F21/567 ,  G06F21/602 ,  G06F21/606 ,  G06F21/85 ,  H04L12/40006 ,  H04L12/40032 ,  H04L63/1408 ,  H04L63/168 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Controller Area Network (CAN) device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and a shield device connected between the CAN bus interface and the microcontroller communications interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from a Serial Peripheral Interface (SPI) interface of the microcontroller communications interface. The shield device is configured to direct CAN Flexible Data-rate (FD) traffic received from the CAN bus interface to the security module.

公开(公告)号：US09590598B2

公开(公告)日：2017-03-07

申请号：US14863369

申请日：2015-09-23

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ralf Malzahn

IPC: H03K3/037 ,  H03K3/3562 ,  H03K3/011

CPC classification number: H03K3/0372 ,  H03K3/011 ,  H03K3/0375 ,  H03K3/35625

Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

Abstract translation: 公开了一种触发器（10），包括从锁存器（30）和主锁存器（20）。 从机和主机锁存器中的每一个包括一对交叉耦合的逻辑门（21,22,31,32）。 从属或主锁存器（30,20）的交叉耦合连接包括布置成将触发器（10）的灵敏度降低到电流注入的电阻元件（8,9,11,12）。

公开(公告)号：US20160342531A1

公开(公告)日：2016-11-24

申请号：US14720132

申请日：2015-05-22

Applicant: NXP B.V.

Inventor： Vibhu Sharma

IPC: G06F12/14 ,  G06F13/42

CPC classification number: G06F12/1408 ,  G06F13/4265 ,  G06F21/567 ,  G06F2212/1052 ,  H04L12/40143 ,  H04L63/1408

Abstract: Embodiments of a device and method are disclosed. In an embodiment, an IVN transceiver is disclosed. The IVN transceiver includes an IVN bus interface, a microcontroller communications interface, and a security module connected between the IVN bus interface and the microcontroller communications interface and configured to perform a security function.

Abstract translation: 公开了一种装置和方法的实施例。 在一个实施例中，公开了一种IVN收发器。 IVN收发器包括IVN总线接口，微控制器通信接口以及连接在IVN总线接口和微控制器通信接口之间并被配置为执行安全功能的安全模块。

公开(公告)号：US09490781B2

公开(公告)日：2016-11-08

申请号：US14265097

申请日：2014-04-29

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

Abstract translation: 描述锁存电路的实施例和操作锁存电路的方法。 在一个实施例中，锁存电路包括被配置为接收输入数据信号的输入端子，被配置为控制输入数据信号的应用的开关单元，连接到开关单元的第一反相器电路，其中第一反相器电路包括第一 交叉耦合对的反相器，以及通过开关单元连接到第一反相器电路的第二反相器电路。 第二逆变器电路包括第二交叉耦合的一对反相器和两个晶体管器件。 第二交叉耦合对的反相器的每个反相器通过相应的晶体管器件连接到电压轨。 两个晶体管器件中的每一个连接到开关单元与第一反相器电路或第二反相器电路之间的节点。 还描述了其它实施例。

公开(公告)号：US09417657B2

公开(公告)日：2016-08-16

申请号：US14504789

申请日：2014-10-02

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: H03K3/00 ,  G06F1/10 ,  H03K5/159 ,  H03K19/094

CPC classification number: G06F1/10 ,  H03K5/159 ,  H03K19/094

Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

Abstract translation: 本公开的方面涉及操作基于时间的电路。 可以结合一个或多个实施例来实现，一种装置和/或方法涉及检测在相应时钟域中工作的电路的定时特性，每个时钟域具有时钟信号路径经过的半导体主体区域。 各个半导体本体区域以各自的偏置电平被偏置，这些偏置电平是基于检测到的偏移半导体主体区域的时钟信号路径的定时特性。

公开(公告)号：US20160087611A1

公开(公告)日：2016-03-24

申请号：US14863369

申请日：2015-09-23

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ralf Malzahn

IPC: H03K3/037 ,  H03K3/011 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  H03K3/011 ,  H03K3/0375 ,  H03K3/35625

Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

Abstract translation: 公开了一种触发器（10），包括从锁存器（30）和主锁存器（20）。 从机和主机锁存器中的每一个包括一对交叉耦合的逻辑门（21,22,31,32）。 从属或主锁存器（30,20）的交叉耦合连接包括布置成将触发器（10）的灵敏度降低到电流注入的电阻元件（8,9,11,12）。

公开(公告)号：US20150346742A1

公开(公告)日：2015-12-03

申请号：US14293785

申请日：2014-06-02

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Ralf Malzahn ,  Vibhu Sharma ,  Jose de Jesus Pineda de Gyvez ,  Peter Thueringer

IPC: G05F1/46

CPC classification number: G05F1/46 ,  G06F1/32

Abstract: A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.

Abstract translation: 一种系统，包括：电压转换器，被配置为将来自电源的电压转换成不同的电压; 耦合到电压转换器的存储器; 数字逻辑电路; 以及耦合在存储器和数字逻辑电路之间的电平移位器; 其中来自所述存储器的泄漏电流被存储在所述数字逻辑电路中的电容中，其中所述电压转换器进一步耦合到所述存储器和数字逻辑电路之间的节点，并且其中所述电压转换器被配置为：监视所述节点处的电压 其中所述节点具有期望的工作电压值; 并且当节点电压从期望的工作电压值变化时调节节点处的电压。

公开(公告)号：US09065439B2

公开(公告)日：2015-06-23

申请号：US14168910

申请日：2014-01-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Rinze Ida Mechtildis Pete Meijer ,  Jose Pineda de Gyvez

IPC: H03K19/0185 ,  H03K19/00 ,  G06F1/10 ,  H03K19/0175

CPC classification number: H03K19/0016 ,  G06F1/10 ,  H03K19/017581 ,  H03K19/018521

Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.

Abstract translation: 在时钟树中使用的可调谐缓冲电路具有并联的多个缓冲器，每个缓冲器具有接地功能，以及与缓冲器并联的旁路开关。 该电路具有连接到电路中的一个缓冲器的正常模式，多个缓冲器的第一低电压模式并联连接而不具有接地功能，缓冲器的第二低电压模式并联到接地功能和旁路模式 。