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    Recycling capacitance energy from active mode to low power mode
    2.
    发明授权
    Recycling capacitance energy from active mode to low power mode 有权

    公开(公告)号：US11163346B2

    公开(公告)日：2021-11-02

    申请号：US16118749

    申请日：2018-08-31

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor ,  Kristof Blutman ,  Juan Diego Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Jurgen Geerlings ,  Hamed Fatemi

    IPC: G06F1/26 ,  G06F1/32 ,  H02M3/07 ,  H02M3/137

    Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

    HUMAN-MACHINE-INTERFACE SYSTEM
    3.
    发明申请
    HUMAN-MACHINE-INTERFACE SYSTEM 审中-公开

    公开(公告)号：US20180300138A1

    公开(公告)日：2018-10-18

    申请号：US15943926

    申请日：2018-04-03

    Applicant: NXP B.V.

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Gonzalo Moro Pérez ,  Hendrik Corporaal

    IPC: G06F9/30 ,  G06N3/063 ,  G06F17/15 ,  G06K9/00 ,  G06K9/62

    Abstract: A human-machine-interface system comprising: register-file-memory, configured to store input-data; a first-processing-element-slice, a second-processing-element-slice, and a controller. Each of the processing-slices comprise: a register configured to store register-data; and a processing-element configured to apply an arithmetic and logic operation on the register-data in order to provide convolution-output-data. The controller is configured to: load input-data from the register-file-memory into the first-register as the first-register-data; and load: (i) input-data from the register-file-memory, or (ii) the first-register-data from the first-register, into the second-register as the second-register-data.

    PROCESSOR AND INSTRUCTION SET
    5.
    发明申请
    PROCESSOR AND INSTRUCTION SET 有权

    公开(公告)号：US20220342669A1

    公开(公告)日：2022-10-27

    申请号：US17658356

    申请日：2022-04-07

    Applicant: NXP B.V.

    Inventor： Paul Wielage ,  Mathias Martinus van Ansem ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

    IPC: G06F9/30 ,  G06F9/445 ,  G06F9/54

    Abstract: A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.

    APPARATUS FOR PROCESSING A SIGNAL
    6.
    发明申请
    APPARATUS FOR PROCESSING A SIGNAL 审中-公开

    公开(公告)号：US20200090040A1

    公开(公告)日：2020-03-19

    申请号：US16566991

    申请日：2019-09-11

    Applicant: NXP B.V. ,  TECHNISCHE UNIVERSITEIT EINDHOVEN

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Emad Ayman Taleb Ibrahim

    IPC: G06N3/08 ,  G06N20/10 ,  G10L15/16 ,  G06F3/01

    Abstract: An apparatus for processing a signal for input to a neural network, the apparatus configured to: receive a signal comprising a plurality of samples of an analog signal over time; determine at least one frame comprising a group of consecutive samples of the signal, wherein the or each frame includes a first number of samples; for each frame, determine a set of correlation values comprising a second number of correlation values, the second number less than the first number, each correlation value of the set of correlation values based on an autocorrelation of the frame at a plurality of different time lags; provide an output based on the set of correlation values corresponding to the or each of the frames for a neural network for one or more of classification of the analog signal by the neural network and training the neural network based on a predetermined classification.

    Event-Based Power Manager
    9.
    发明申请
    Event-Based Power Manager 审中-公开

    公开(公告)号：US20190146566A1

    公开(公告)日：2019-05-16

    申请号：US15813861

    申请日：2017-11-15

    Applicant: NXP B.V.

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Manuele Rusci ,  Luca Benini ,  Elisabetta Farella ,  Davide Rossi

    IPC: G06F1/32 ,  G06F11/34 ,  G06F9/48

    Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.

    Level shifter circuit with transistor drive strength variation compensation
    10.
    发明授权
    Level shifter circuit with transistor drive strength variation compensation 有权

    公开(公告)号：US10270448B1

    公开(公告)日：2019-04-23

    申请号：US15980882

    申请日：2018-05-16

    Applicant: NXP B.V.

    Inventor： Kristof Blutman ,  Sebastien Antonius Josephus Fabrie ,  Juan Diego Echeverri Escobar ,  Ajay Kapoor ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

    IPC: H03K19/0185

    Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.

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