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公开(公告)号：US20220342669A1
公开(公告)日：2022-10-27
申请号：US17658356
申请日：2022-04-07
申请人： NXP B.V.
摘要： A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.
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公开(公告)号：US10698007B2
公开(公告)日：2020-06-30
申请号：US15612550
申请日：2017-06-02
申请人： NXP B.V.
发明人： Fred Mostert , Gertjan van Holland , Paul Wielage
IPC分类号： G01R17/02 , H03F3/217 , H04R3/00 , G01R31/28 , H03F3/181 , H03M1/12 , G01R27/16 , H03M1/66 , G01R31/00
摘要： A method and apparatus of load detection for an audio amplifier system is described. A load detector includes a first load terminal and a second load terminal; a controller coupled to the first and second load terminals and configured to in a first control loop, vary a first current supplied to a first load terminal dependent on the difference between a first reference signal and the detected first load terminal voltage; and in a second control loop, vary a second current supplied to the second load terminal dependent on the difference between a second reference signal and the detected second load terminal voltage; and to determine a current through a load connected between the first load terminal and the second load terminal from the second current value, and a voltage across the load from the detected voltage difference between the first load terminal voltage and the second load terminal voltage.
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公开(公告)号：US20240219453A1
公开(公告)日：2024-07-04
申请号：US18149536
申请日：2023-01-03
申请人： NXP B.V.
发明人： Jan-Peter Schat , Paul Wielage
IPC分类号： G01R31/28
CPC分类号： G01R31/2837 , G01R31/2841 , G01R31/2843
摘要： Various embodiments relate to a method of testing a plurality of devices of the same type wherein each of the plurality of devices of the same type include a built-in self-test device, including: randomly generating, by a processor, stimulus parameters; applying, by the built-in self-test devices, the generated stimulus parameters N times to the plurality of devices of the same type; measuring, by the plurality of devices of the same type, a response of the plurality of devices of the same type to the generated stimulus parameters to produce M×N response outputs, where M is a number of the plurality of devices of the same type; calculating, by the processor, a defect likelihood for a test set of the plurality of identical devices based upon a mean of a reference set of the plurality of identical devices response outputs, a mean of the test set response outputs, a standard deviation of reference set response outputs, and a standard deviation of the test set response outputs; determining, by the processor, that the defect likelihood for the test set is greater than a first threshold value; applying, by the processor, an initial step of a directed random search algorithm to update stimulus parameters in response to determining that the defect likelihood is greater than the first threshold; applying, by the built-in self-test devices, the updated stimulus parameters N times to the plurality of devices of the same type; measuring, by the plurality of devices of the same type, a response of the plurality of devices of the same type to the updated stimulus parameters to produce M×N updated response outputs; calculating, by the processor, a defect likelihood for the test set based upon a mean of the reference set updated response outputs, a mean of the test set updated response outputs, a standard deviation of reference set updated response outputs, and a standard deviation of the test set updated response outputs; and determining, by the processor, that the defect likelihood for the test set is greater than a second threshold, wherein the second threshold is greater than the first threshold.
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公开(公告)号：US20240134647A1
公开(公告)日：2024-04-25
申请号：US18483064
申请日：2023-10-09
申请人： NXP B.V.
发明人： Paul Wielage , Ayoub Rifai , Dominique Delbecq
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30098
摘要： A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.
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公开(公告)号：US20170350923A1
公开(公告)日：2017-12-07
申请号：US15612550
申请日：2017-06-02
申请人： NXP B.V.
发明人： Fred Mostert , Gertjan van Holland , Paul Wielage
CPC分类号： G01R17/02 , G01R27/16 , G01R31/006 , G01R31/2825 , H03F3/181 , H03F3/217 , H03F2200/03 , H03F2200/165 , H03F2200/471 , H03M1/12 , H03M1/66 , H04R3/00 , H04R2420/05
摘要： A method and apparatus of load detection for an audio amplifier system is described. A load detector includes a first load terminal and a second load terminal; a controller coupled to the first and second load terminals and configured to in a first control loop, vary a first current supplied to a first load terminal dependent on the difference between a first reference signal and the detected first load terminal voltage; and in a second control loop, vary a second current supplied to the second load terminal dependent on the difference between a second reference signal and the detected second load terminal voltage; and to determine a current through a load connected between the first load terminal and the second load terminal from the second current value, and a voltage across the load from the detected voltage difference between the first load terminal voltage and the second load terminal voltage.
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公开(公告)号：US11995442B2
公开(公告)日：2024-05-28
申请号：US17658356
申请日：2022-04-07
申请人： NXP B.V.
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152
摘要： A processor includes a register file having a plurality of register file addresses, a processing unit, configured to perform processing in accordance with a configuration defined by information stored in the register file, and an instruction sequencer. The instruction sequencer is configured to control the processing unit by retrieving a sequence of instructions from a memory, in which each instruction includes an opcode, and a subset of the instructions includes a data portion. For each instruction in the sequence of instructions, the instruction sequencer performs an action defined by the opcode. The action for the subset of the opcodes includes writing the data portion to a register file address defined by the opcode. The sequence of instructions includes variable length instructions.
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