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公开(公告)号:US10732698B2
公开(公告)日:2020-08-04
申请号:US15813861
申请日:2017-11-15
Applicant: NXP B.V.
Inventor: Jose de Jesus Pineda de Gyvez , Hamed Fatemi , Manuele Rusci , Luca Benini , Elisabetta Farella , Davide Rossi
IPC: G06F1/32 , G06F1/324 , G06F11/34 , G06F9/48 , G06F1/3228 , G06F1/329 , G06F1/3234
Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.
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公开(公告)号:US20190146566A1
公开(公告)日:2019-05-16
申请号:US15813861
申请日:2017-11-15
Applicant: NXP B.V.
Inventor: Jose de Jesus Pineda de Gyvez , Hamed Fatemi , Manuele Rusci , Luca Benini , Elisabetta Farella , Davide Rossi
Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.
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