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    Method for manufacturing a semiconductor structure
    12.
    发明授权
    Method for manufacturing a semiconductor structure 有权

    公开(公告)号：US10431559B2

    公开(公告)日：2019-10-01

    申请号：US15851572

    申请日：2017-12-21

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Po Chun Lin

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

    Semiconductor structure and a manufacturing method thereof
    13.
    发明授权
    Semiconductor structure and a manufacturing method thereof 有权

    公开(公告)号：US10170339B2

    公开(公告)日：2019-01-01

    申请号：US15333933

    申请日：2016-10-25

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Po Chun Lin

    IPC: H01L23/31 ,  H01L21/56 ,  H01L23/28

    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and a chip disposed over the substrate; disposing the substrate over a first molding member; disposing a second molding member over the substrate to encapsulate the chip; disposing a molding material around the chip; forming a molding over the substrate and around the chip; removing the first molding member; removing the second molding member; wherein the first molding member includes a curved surface protruded towards the substrate, the chip or the second molding member.

    Method for manufacturing a semiconductor structure
    14.
    发明授权
    Method for manufacturing a semiconductor structure 有权

    公开(公告)号：US10141275B2

    公开(公告)日：2018-11-27

    申请号：US15851186

    申请日：2017-12-21

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Po Chun Lin

    IPC: H01L23/00

    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

    Chip package
    16.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US09252105B2

    公开(公告)日：2016-02-02

    申请号：US14155590

    申请日：2014-01-15

    Applicant: NANYA TECHNOLOGY CORPORATION

    Inventor： Po Chun Lin

    IPC: H01L29/40 ,  H01L23/538 ,  H01L25/07 ,  H01L23/522

    CPC classification number: H01L23/5384 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/5386 ,  H01L25/0657 ,  H01L25/074 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06565

    Abstract: A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections.

    Abstract translation: 芯片封装的芯片包括具有芯片电路的基板，连接到芯片电路的芯片选择端子，由多个绝缘层在不同级别分离的多个第一导体，分别连接到第一导体并延伸到第一导体的多个第一垂直连接 衬底表面，分别连接到第一导体并延伸到绝缘层的表面的多个第二垂直连接，电连接到芯片选择端子并延伸到衬底表面的第三垂直连接;穿过绝缘层形成的第四垂直连接 并且所述基板，形成在所述绝缘层的表面上并连接到所述第四垂直连接的第二导体，分别连接到所述第一垂直连接和所述第三垂直连接的多个第一焊盘以及分别连接到所述第二垂直连接的多个第二焊盘 。

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