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    Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof
    11.
    发明授权
    Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof 失效
    在测试模式下可操作的动态半导体存储器件及其功能的测试方法

    公开(公告)号：US5208778A

    公开(公告)日：1993-05-04

    申请号：US739736

    申请日：1991-07-30

    Applicant: Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Yoshinori Inoue

    Inventor： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Yoshinori Inoue

    IPC: G11C29/36

    CPC classification number: G11C29/36

    Abstract: A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

    Abstract translation: 动态型半导体存储器件具有在多个位的存储单元上同时执行功能测试的测试模式。 在测试模式下的数据写入中，从写入数据反转的数据被写入到同时选择的多个存储单元中的至少1位存储单元中，与写入数据相同的数据是 写在剩余的存储单元中。 在测试模式下的数据读取中，将反转数据写入的同时选择的存储单元的数据进行反转和读取，而剩余存储单元的数据原样读取。 对多个位的读出数据执行逻辑处理，从而根据关于读出的数据是否为0的确定结果输出表示半导体存储器件的可接受性的逻辑值 相同。

    Semiconductor memory device having shared sense amplifier and operating method thereof
    13.
    发明授权
    Semiconductor memory device having shared sense amplifier and operating method thereof 失效
    具有共享读出放大器的半导体存储器件及其操作方法

    公开(公告)号：US5014246A

    公开(公告)日：1991-05-07

    申请号：US435901

    申请日：1989-11-14

    Applicant: Takahiro Komatsu ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yoshinori Inoue

    Inventor： Takahiro Komatsu ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yoshinori Inoue

    IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4091

    CPC classification number: G11C11/4091

    Abstract: A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).

    Abstract translation: 存储单元阵列（10）被分成四个块。 每个块包括存储单元阵列块（10a和存储单元阵列块），读出放大器块（20）设置在存储单元阵列块（10a）和（10b）之间，每个读出放大器块（20）是 分别经由开关电路（80a，80b）连接到存储单元阵列块（10a）和（10b），四个解码器（51）分别对应于四个块，四个解码器（51）通常配置有驱动器 （52）产生高电平驱动信号，每个解码器（51）响应于地址信号，用于将来自驱动器（52）的驱动信号提供给开关电路（80a，80b）中的任一个并且用于施加地电位 因此，读出放大器块（20）连接到存储单元阵列块（10a，10b）中的任意一个。

    Dynamic semiconductor memory device and method for controllig the precharge/refresh and access modes thereof
    15.
    发明授权
    Dynamic semiconductor memory device and method for controllig the precharge/refresh and access modes thereof 失效
    动态半导体存储器件和用于控制其预充电/刷新和存取模式的方法

    公开(公告)号：US4907199A

    公开(公告)日：1990-03-06

    申请号：US271489

    申请日：1988-11-15

    Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu

    Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu

    IPC: G11C11/409 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4094

    CPC classification number: G11C11/4094 ,  G11C11/406

    Abstract: A dynamic semiconductor memory device is divided into a plurality of blocks. An operation of the semiconductor memory device is in either of a normal mode and a refresh mode, depending on the level of a refresh signal. In the normal mode, at an off time period, a potential on a bit line pair is equalized and a precharge potential is applied to the bit line pair. At the access time, equalizing of the potential on the bit line pair and supply of the precharge potential are stopped in a selected block and then, a word line driving signal is raised. On the other hand, in the refresh mode, at the off time period, the potential on the bit line pair is held at "H" and "L" levels by a sense amplifier, so that the potential on the bit line pair is not equalized and the precharge potential is not supplied. On this occasion, a precharge potential generating circuit is electrically disconnected from a power supply. At the time of refresh operation, the sense amplifier is rendered inactive in the selected block, so that the potential on the bit line pair is equalized and then, the word line driving signal is raised.

    Abstract translation: 动态半导体存储器件被分成多个块。 根据刷新信号的电平，半导体存储器件的操作是正常模式和刷新模式。 在正常模式下，在关闭时间段，位线对上的电位被均衡，并且预充电电位被施加到位线对。 在访问时间，在所选择的块中停止位线对上的电位的均衡和预充电电势的供给，然后提高字线驱动信号。 另一方面，在刷新模式下，在关闭时间段，位线对上的电位由读出放大器保持在“H”和“L”电平，使得位线对上的电位不是 均衡，不提供预充电电位。 在这种情况下，预充电电位产生电路与电源电气断开。 在刷新操作时，读出放大器在所选择的块中变为无效，使位线对上的电位相等，然后提高字线驱动信号。

    Semiconductor memory device with an improved multi-bit test mode
    16.
    发明授权
    Semiconductor memory device with an improved multi-bit test mode 失效
    具有改进的多位测试模式的半导体存储器件

    公开(公告)号：US4899313A

    公开(公告)日：1990-02-06

    申请号：US178427

    申请日：1988-04-06

    Applicant: Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Yasuhiro Konishi

    Inventor： Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Yasuhiro Konishi

    IPC: G11C29/00 ,  G06F12/16 ,  G11C29/34

    CPC classification number: G11C29/34

    Abstract: A memory device provides a test mode which simultaneously carries out the function test of plural bit memory cells. In this memory device, trilevel decision is carried out based on the AND operation on the memory cell information of the selected plural bits in the single device level while bilevel decision is carried out in the board level on the basis of the OR operation on the AND result of the information of the selected plural bit memory cells and the AND result of the inverted information of the same.

    Abstract translation: 存储器件提供同时进行多位存储器单元的功能测试的测试模式。 在该存储器件中，基于对单个器件电平中所选择的多个位的存储单元信息的AND运算进行三级判定，而基于AND上的OR运算在电路板级进行双电位判定 所选择的多位存储单元的信息的结果和其反相信息的与结果。

    Vehicle maneuver assistance device
    18.
    发明授权
    Vehicle maneuver assistance device 有权
    车辆操纵辅助装置

    公开(公告)号：US08340870B2

    公开(公告)日：2012-12-25

    申请号：US12584734

    申请日：2009-09-11

    Applicant: Kenichi Ohshima ,  Yukihiro Fujiwara ,  Yoshitaka Katashima ,  Hiroyuki Kawagoe ,  Shigenobu Saigusa ,  Yasushi Shoda ,  Manabu Shimizu ,  Yasuhiro Konishi

    Inventor： Kenichi Ohshima ,  Yukihiro Fujiwara ,  Yoshitaka Katashima ,  Hiroyuki Kawagoe ,  Shigenobu Saigusa ,  Yasushi Shoda ,  Manabu Shimizu ,  Yasuhiro Konishi

    IPC: G06F7/00

    CPC classification number: B62D15/0275 ,  B60R1/00 ,  B60R2300/105 ,  B60R2300/303 ,  B60R2300/305 ,  B60R2300/607 ,  B60R2300/806 ,  B62D15/028

    Abstract: The vehicle maneuver assistance device includes: a plurality of external environment imaging units; a converter that performs a view point conversion; a display unit provided in an interior of the present-vehicle; a steering angle status value detector which detects status values of the steering angle representing an actual steering angle of the present-vehicle, and outputs a steering angle status value; a display controller that causes the display unit to display the converted image, and, overlaid thereon, a guidance display which assists a parking maneuver of the present-vehicle, wherein the display controller controls the guidance display according to the steering angle status value, so that the guidance display includes: an initial positioning guide line representing an initial location of the present-vehicle at the beginning of the parking maneuver; and a steering-switching start positioning guide line representing a starting location of a quick steering direction switching.

    Abstract translation: 车辆操纵辅助装置包括：多个外部环境成像单元; 执行视点转换的转换器; 设置在本车内部的显示单元; 转向角状态值检测器，其检测表示本车辆的实际转向角的转向角的状态值，并输出转向角状态值; 显示控制器，其使显示单元显示转换的图像，并且覆盖有辅助本车的停车操作的引导显示，其中显示控制器根据转向角状态值来控制引导显示，因此， 引导显示包括：在停车操作开始时代表当前车辆的初始位置的初始定位引导线; 以及表示快速转向方向切换的起始位置的转向切换开始定位引导线。

    Semiconductor memory device enabling selective production of different semiconductor memory devices operating at different external power-supply voltages
    19.
    发明授权
    Semiconductor memory device enabling selective production of different semiconductor memory devices operating at different external power-supply voltages 失效
    半导体存储器件能够选择性地生产在不同外部电源电压下工作的不同半导体存储器件

    公开(公告)号：US06501671B2

    公开(公告)日：2002-12-31

    申请号：US09793996

    申请日：2001-02-28

    Applicant: Yasuhiro Konishi

    Inventor： Yasuhiro Konishi

    IPC: G11C506

    CPC classification number: G11C5/147 ,  G11C5/14

    Abstract: Common circuit includes inactivation/activation circuits. Exclusive circuits include inverters IV3, IV4, IV5 and IV6 at the input portions thereof. When an SDR-SDRM is to be produced, inactivation/activation circuit outputs an inactivation signal DASL fixed to a ground voltage to exclusive circuit, while inactivation/activation circuit outputs a signal /OE inverted from an output enable signal OE to exclusive circuit. Inverters IV5 and IV6 in exclusive circuit then output a signal based on the signal /OE. Further, an N-channel MOS transistor and a P-channel MOS transistor in exclusive circuit are completely turned off, so that no through current flows from a power-supply node to a ground terminal in exclusive circuit. As a result, generation of the through current is prevented in an inactivated circuit.

    Abstract translation: 公共电路包括灭活/激活电路。 专用电路在其输入部分包括反相器IV3，IV4，IV5和IV6。 当要生成SDR-SDRM时，灭活/激活电路将固定为接地电压的失活信号DASL输出到专用电路，而灭活/激活电路将从输出使能信号OE反相的信号/ OE输出到专用电路。 独占电路中的逆变器IV5和IV6然后基于信号/ OE输出信号。 此外，专用电路中的N沟道MOS晶体管和P沟道MOS晶体管完全截止，从而在专用电路中，不会从电源节点流向接地端子。 结果，在非激活电路中防止通过电流的产生。

    Semiconductor memory device
    20.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06449198B1

    公开(公告)日：2002-09-10

    申请号：US09717375

    申请日：2000-11-22

    Applicant: Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

    Inventor： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

    IPC: G11C700

    CPC classification number: G11C7/1048 ,  G11C11/4096 ,  G11C11/4097

    Abstract: In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

    Abstract translation: 在SDRAM中，选择器根据列块选择信号和字配置选择信号来选择四个全局IO线对中的一个，并将所选择的全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对 在规定的时间内。 由于全局IO线对的均衡可以在全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对之后立即开始，所以可以将全局IO线的更长的均衡周期放在一边，以便 读取操作可以稳定。

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