公开(公告)号：US07298005B2

公开(公告)日：2007-11-20

申请号：US11342524

申请日：2006-01-31

Applicant: Susumu Yoshikawa

Inventor： Susumu Yoshikawa

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11519

Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.

公开(公告)号：US5013679A

公开(公告)日：1991-05-07

申请号：US403292

申请日：1989-09-05

Applicant: Jumpei Kumagai ,  Susumu Yoshikawa

Inventor： Jumpei Kumagai ,  Susumu Yoshikawa

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10844 ,  H01L27/10829

Abstract: In a cell capacitor of a dynamic random access memory cell according to the present invention, an insulation film is formed on the surface of a fine trench formed in a silicon semiconductor substrate. A contact hole is formed in the insulation film in a region on the side wall of the trench. A polysilicon film is formed on the side wall of the trench in a hollow-cylindrical shape. A silicon layer is epitaxially and selectively grown on the polysilicon film and on the silicon substrate exposed through the contact hole. The polysilicon film and the silicon layer constitute an information storage electrode. At least the silicon layer of the information storage electrode is electrically connected to a source or a drain region of a transfer transistor of the memory cell. A gate insulation film is formed on the surface of the silicon layer. A counter electrode is formed such that the counter electrode is embedded in the trench.

Abstract translation: 在根据本发明的动态随机存取存储单元的单元电容器中，在形成在硅半导体衬底中的细沟槽的表面上形成绝缘膜。 在沟槽的侧壁上的区域中的绝缘膜中形成接触孔。 在中空圆柱形状的沟槽的侧壁上形成多晶硅膜。 硅层被外延选择性地生长在多晶硅膜上并通过接触孔暴露的硅衬底上。 多晶硅膜和硅层构成信息存储电极。 至少信息存储电极的硅层电连接到存储单元的转移晶体管的源极或漏极区域。 在硅层的表面上形成栅极绝缘膜。 形成对电极使得对电极嵌入沟槽中。

公开(公告)号：US4916521A

公开(公告)日：1990-04-10

申请号：US223971

申请日：1988-07-25

Applicant: Susumu Yoshikawa ,  Shizuo Sawada

Inventor： Susumu Yoshikawa ,  Shizuo Sawada

IPC: H01L21/768 ,  H01L23/485

CPC classification number: H01L23/485 ,  H01L2924/0002

Abstract: A first insulation layer is formed on a semiconductor substrate, and a first conductive layer is formed on the first insulation layer. A second insulation layer is formed on the first conductive layer and the first insulation layer, and a first contact hole, having a width greater than that of the first conductive layer, is formed in the second insulation layer, at a position corresponding to the first conductive layer. A second conductive layer, having a width greater than that of the first contact hole, is formed on the second insulation layer and in the first contact hole, and is formed in contact with the upper and side surfaces of the first conductive layer located inside the second contact hole. A third insulation layer is formed on the second conductive layer and the second insulation layer, and a second contact hole, having a width less than that of the second conductive layer, is formed in the third insulation layer, at a position corresponding to the second conductive layer. A third conductive layer, having a width greater than that of the second contact hole but less than that of the second conductive layer, is formed on the third conductive layer and in the second contact hole. The first conductive layer is electrically connected to the third conductive layer.

Abstract translation: 在半导体衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层。 第二绝缘层形成在第一导电层和第一绝缘层上，并且具有大于第一导电层的宽度的第一接触孔形成在第二绝缘层中的与第一绝缘层相对应的位置处的第一绝缘层 导电层。 在第二绝缘层和第一接触孔中形成具有大于第一接触孔的宽度的第二导电层，并且形成为与位于第一接触孔内部的第一导电层的上表面和侧表面接触 第二接触孔。 在第二绝缘层上形成第三绝缘层，第二绝缘层和宽度小于第二导电层宽度的第二接触孔形成在第三绝缘层中，对应于第二绝缘层的第二绝缘层 导电层。 在第三导电层和第二接触孔中形成具有大于第二接触孔的宽度但小于第二导电层的宽度的第三导电层。 第一导电层电连接到第三导电层。

公开(公告)号：US20140014882A1

公开(公告)日：2014-01-16

申请号：US13980159

申请日：2012-01-17

Applicant: Toshinobu Ohno ,  Yuko Takao ,  Kazuyuki Moriwaki ,  Fukashi Matsumoto ,  Takatoshi Ito ,  Toshiyuki Iwai ,  Susumu Yoshikawa ,  Takashi Sagawa ,  Soichi Uchida ,  Satoru Ikeda

Inventor： Toshinobu Ohno ,  Yuko Takao ,  Kazuyuki Moriwaki ,  Fukashi Matsumoto ,  Takatoshi Ito ,  Toshiyuki Iwai ,  Susumu Yoshikawa ,  Takashi Sagawa ,  Soichi Uchida ,  Satoru Ikeda

IPC: H01L51/00

CPC classification number: H01L51/0047 ,  B82Y10/00 ,  C07C43/21 ,  C07C2604/00 ,  H01L51/424 ,  H01L51/4253 ,  Y02E10/549

Abstract: The present invention provides a fullerene derivative having an electron donating group adjacent to the fullerene nucleus, represented by formula (I) which exhibits a high LUMO energy and a high open circuit voltage based thereon and which is highly compatible with polymers and excellent in charge mobility and charge separation ability: wherein the encircled FL represents fullerene C60 or C70, Donor-Sub represents a substituent having at least one electron donating substituent atom located at a position apart from the fullerene nucleus by two bonds, R is hydrogen, Donor-Sub, an alkyl, cycloalkyl, alkoxy, alkoxy-substituted alkyl, alkoxy-substituted alkoxy, alkylthio-substituted alkoxy, alkylthio, alkylthio-substituted alkylthio, or alkoxy-substituted alkylthio group, having a total carbon atoms of 1 or more and 20 or fewer, or a benzyl or phenyl group, and n is an integer of 1 to 10.

Abstract translation: 本发明提供具有与富勒烯核相邻的给电子基团的富勒烯衍生物，由式（I）表示，其表现出高的LUMO能量和基于其的高开路电压，并且与聚合物高度相容并且具有优异的电荷迁移率 和电荷分离能力：其中包围的FL表示富勒烯C60或C70，Donor-Sub表示具有至少一个给电子取代基原子的取代基，该取代基位于离富勒烯核离开两个位置的位置，R为氢，Donor-Sub， 烷基，环烷基，烷氧基，烷氧基取代的烷基，烷氧基取代的烷氧基，烷硫基取代的烷氧基，烷硫基，烷硫基取代的烷硫基或烷氧基取代的烷硫基，总碳原子数为1以上且20以下， 或苄基或苯基，n为1〜10的整数。

公开(公告)号：US08044450B2

公开(公告)日：2011-10-25

申请号：US11174536

申请日：2005-07-06

Applicant: Mitsuhiro Noguchi ,  Susumu Yoshikawa ,  Koichi Fukuda

Inventor： Mitsuhiro Noguchi ,  Susumu Yoshikawa ,  Koichi Fukuda

IPC: H01L29/788

CPC classification number: H01L27/105 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.

Abstract translation: 包括具有高电阻和高电阻精度的电阻元件和非易失性半导体存储元件的半导体器件通过包括非易失性半导体存储元件被合理地实现，所述非易失性半导体存储元件包括形成为隔离第一半导体区域的第一隔离，第一绝缘体 以及自对准方式的第一电极和第二电极，并且所述电阻元件包括形成为以自对准的方式隔离第二半导体区域，第三绝缘体和导体层的第二隔离，以及第三和 第四电极通过第四绝缘体形成在导体层的每个端部上，并与导体层连接。 导体层或第三和第四电极分别包括与第一或第二电极相同的材料。

公开(公告)号：US20060220003A1

公开(公告)日：2006-10-05

申请号：US11174536

申请日：2005-07-06

Applicant: Mitsuhiro Noguchi ,  Susumu Yoshikawa ,  Koichi Fukuda

Inventor： Mitsuhiro Noguchi ,  Susumu Yoshikawa ,  Koichi Fukuda

IPC: H01L29/06

CPC classification number: H01L27/105 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device comprising a resistance element with a high resistance and high resistance accuracy and a non-volatile semiconductor storage element is rationally realized by comprising the non-volatile semiconductor storage element comprising a first isolation formed to isolate a first semiconductor area, a first insulator, and a first electrode in a self-aligned manner, and a second electrode, and the resistance element comprising a second isolation formed to isolate a second semiconductor area, a third insulator and a conductor layer in a self-aligned manner, and third and fourth electrodes formed on each end of the conductor layer via a fourth insulator, and connected with the conductor layer. The conductor layer or the third and fourth electrodes include the same material with the first or second electrode, respectively.

Abstract translation: 包括具有高电阻和高电阻精度的电阻元件和非易失性半导体存储元件的半导体器件通过包括非易失性半导体存储元件被合理地实现，所述非易失性半导体存储元件包括形成为隔离第一半导体区域的第一隔离，第一绝缘体 以及自对准方式的第一电极和第二电极，并且所述电阻元件包括形成为以自对准的方式隔离第二半导体区域，第三绝缘体和导体层的第二隔离，以及第三和 第四电极通过第四绝缘体形成在导体层的每个端部上，并与导体层连接。 导体层或第三和第四电极分别包括与第一或第二电极相同的材料。

公开(公告)号：US06776918B1

公开(公告)日：2004-08-17

申请号：US09720450

申请日：2000-12-08

Applicant: Susumu Yoshikawa ,  Yuko Tanaka ,  Teruki Takayasu ,  Hiromasa Ogawa ,  Kinji Onoda ,  Masatada Makino ,  Takashi Nishiyama

Inventor： Susumu Yoshikawa ,  Yuko Tanaka ,  Teruki Takayasu ,  Hiromasa Ogawa ,  Kinji Onoda ,  Masatada Makino ,  Takashi Nishiyama

IPC: C23F302

CPC classification number: B32B15/08 ,  B32B7/12 ,  B32B2311/18 ,  B32B2398/20 ,  C23F1/26

Abstract: The invention provides a titanium composite material comprising a bonded laminate having a layer of macromolecular material bonded to the modified surface of a titanium sheet or a titanium alloy sheet, and a process for preparing a titanium composite material, the process comprising the step of bonding a macromolecular material to a titanium sheet or a titanium alloy sheet having a modified surface to be bonded.

Abstract translation: 本发明提供一种钛复合材料，其包含具有与钛片或钛合金片的改性表面结合的高分子材料层的接合层叠体，以及钛复合材料的制造方法，该方法包括将 高分子材料加工成具有待结合的改性表面的钛片或钛合金片。

公开(公告)号：US06187391B1

公开(公告)日：2001-02-13

申请号：US09218029

申请日：1998-12-22

Applicant: Seiichi Kataoka ,  Susumu Yoshikawa

Inventor： Seiichi Kataoka ,  Susumu Yoshikawa

IPC: B05D500

CPC classification number: D06M15/09 ,  D06M10/025 ,  D06M14/04 ,  D06M14/08 ,  D06M15/03 ,  D06M15/05 ,  D06M15/11 ,  D06M15/13 ,  D06M15/263 ,  D06M15/333 ,  D06M23/16 ,  Y10T442/2049 ,  Y10T442/2057 ,  Y10T442/2066

Abstract: Provided is a method for modifying one surface of a textile fabric or a nonwoven fabric, which comprises coating a sizing agent inactive to plasma treatment on one surface of a hydrophobic or hydrophilic textile fabric or nonwoven fabric, subjecting another surface of the textile fabric or the nonwoven fabric to low-temperature plasma treatment to form an active seed for a graft polymerization reaction, then graft-polymerizing this active seed with a polymerizable monomer, and thereafter removing the sizing agent coated on one surface of the textile fabric or the nonwoven fabric. Clothing in which sweat given in sports or the like can easily be shifted from one surface to another thereof and can easily be evaporated and which has wash and wear properties is obtained.

Abstract translation: 本发明提供一种改性织物或非织造织物的一个表面的方法，该方法包括在疏水或亲水纺织织物或非织造织物的一个表面上涂覆对等离子体处理无活性的施胶剂，对织物的另一表面或 无纺织物进行低温等离子体处理以形成接枝聚合反应的活性种子，然后将该活性种子与可聚合单体接枝聚合，然后除去涂布在纺织品或非织造织物的一个表面上的施胶剂。 可以容易地将运动等中给予的汗液从一个表面转移到另一个表面的衣服，并且可以容易地蒸发并获得具有洗涤和磨损性能的衣服。

公开(公告)号：US5384473A

公开(公告)日：1995-01-24

申请号：US953808

申请日：1992-09-30

Applicant: Susumu Yoshikawa ,  Akira Sudo

Inventor： Susumu Yoshikawa ,  Akira Sudo

IPC: H01L21/02 ,  H01L21/18 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L27/02 ,  H01L27/04 ,  H01L29/04

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/187 ,  H01L21/31658 ,  H01L21/76205 ,  H01L21/76294 ,  H01L21/823892 ,  H01L27/0928 ,  H01L27/11

Abstract: A semiconductor body has a first and a second element formation surface. The semiconductor body is constructed in such a manner that a first semiconductor substrate, which has a first main surface at which the plane appears, is laminated to a second semiconductor substrate, which has a second main surface at which the plane appears. Made in the first semiconductor substrate is at least one opening at which the second main surface of the second semiconductor substrate. The first main surface of the first semiconductor substrate becomes the first element formation surface of the semiconductor body, and the second main surface of the second semiconductor substrate becomes the second element formation surface of the body.

Abstract translation: 半导体本体具有第一和第二元件形成表面。 半导体本体被构造成使具有出现平面的第一主表面的第一半导体衬底被层压到第二半导体衬底上，第二半导体衬底具有出现平面的第二主表面。 在第一半导体衬底中制造的是至少一个第二半导体衬底的第二主表面的开口。 第一半导体衬底的第一主表面成为半导体本体的第一元件形成表面，第二半导体衬底的第二主表面成为主体的第二元件形成表面。

公开(公告)号：US09287506B2

公开(公告)日：2016-03-15

申请号：US13980159

申请日：2012-01-17

Applicant: Toshinobu Ohno ,  Yuko Takao ,  Kazuyuki Moriwaki ,  Fukashi Matsumoto ,  Takatoshi Ito ,  Toshiyuki Iwai ,  Susumu Yoshikawa ,  Takashi Sagawa ,  Soichi Uchida ,  Satoru Ikeda

Inventor： Toshinobu Ohno ,  Yuko Takao ,  Kazuyuki Moriwaki ,  Fukashi Matsumoto ,  Takatoshi Ito ,  Toshiyuki Iwai ,  Susumu Yoshikawa ,  Takashi Sagawa ,  Soichi Uchida ,  Satoru Ikeda

IPC: H01B1/04 ,  H01L51/00 ,  B82Y30/00 ,  B82Y10/00 ,  C07C43/21 ,  H01L51/42

CPC classification number: H01L51/0047 ,  B82Y10/00 ,  C07C43/21 ,  C07C2604/00 ,  H01L51/424 ,  H01L51/4253 ,  Y02E10/549

Abstract: The present invention provides a fullerene derivative having an electron donating group adjacent to the fullerene nucleus, represented by formula (I) which exhibits a high LUMO energy and a high open circuit voltage based thereon and which is highly compatible with polymers and excellent in charge mobility and charge separation ability: wherein the encircled FL represents fullerene C60 or C70, Donor-Sub represents a substituent having at least one electron donating substituent atom located at a position apart from the fullerene nucleus by two bonds, R is hydrogen, Donor-Sub, an alkyl, cycloalkyl, alkoxy, alkoxy-substituted alkyl, alkoxy-substituted alkoxy, alkylthio-substituted alkoxy, alkylthio, alkylthio-substituted alkylthio, or alkoxy-substituted alkylthio group, having a total carbon atoms of 1 or more and 20 or fewer, or a benzyl or phenyl group, and n is an integer of 1 to 10.

Abstract translation: 本发明提供具有与富勒烯核相邻的给电子基团的富勒烯衍生物，由式（I）表示，其表现出高的LUMO能量和基于其的高开路电压，并且与聚合物高度相容并且具有优异的电荷迁移率 和电荷分离能力：其中包围的FL表示富勒烯C60或C70，Donor-Sub表示具有至少一个给电子取代基原子的取代基，该取代基位于离富勒烯核离开两个位置的位置，R为氢，Donor-Sub， 烷基，环烷基，烷氧基，烷氧基取代的烷基，烷氧基取代的烷氧基，烷硫基取代的烷氧基，烷硫基，烷硫基取代的烷硫基或烷氧基取代的烷硫基，总碳原子数为1以上且20以下， 或苄基或苯基，n为1〜10的整数。