公开(公告)号：US12068415B2

公开(公告)日：2024-08-20

申请号：US17966817

申请日：2022-10-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78642 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20230029561A1

公开(公告)日：2023-02-02

申请号：US17966817

申请日：2022-10-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US11257681B2

公开(公告)日：2022-02-22

申请号：US16514235

申请日：2019-07-17

Applicant: International Business Machines Corporation

Inventor： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L27/092

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

公开(公告)号：US20210391473A1

公开(公告)日：2021-12-16

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US11024551B1

公开(公告)日：2021-06-01

申请号：US16735857

申请日：2020-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Somnath Ghosh ,  Carl Radens

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.

公开(公告)号：US11977614B2

公开(公告)日：2024-05-07

申请号：US17479623

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Hsueh-Chung Chen

IPC: G06F30/00 ,  G06F21/16 ,  G06F30/20 ,  G06F30/30 ,  H05K3/00

CPC classification number: G06F21/16 ,  G06F30/00 ,  G06F30/20 ,  G06F30/30 ,  H05K3/00

Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

公开(公告)号：US20230090521A1

公开(公告)日：2023-03-23

申请号：US17479623

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Hsueh-Chung Chen

IPC: G06F21/16

Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

公开(公告)号：US11527434B2

公开(公告)日：2022-12-13

申请号：US16796079

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Daniel James Dechene ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

公开(公告)号：US11515427B2

公开(公告)日：2022-11-29

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20220069104A1

公开(公告)日：2022-03-03

申请号：US17521964

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.