公开(公告)号：US20230317140A1

公开(公告)日：2023-10-05

申请号：US17708448

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Rajabali Koduri ,  Pushkar Ranade ,  Wilfred Gomes

IPC: G11C11/408 ,  G11C11/4094 ,  H03K19/17728 ,  H03K19/0185

CPC classification number: G11C11/4087 ,  G11C11/4094 ,  G11C11/4085 ,  H03K19/17728 ,  H03K19/018521

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

公开(公告)号：US20230275067A1

公开(公告)日：2023-08-31

申请号：US17680368

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/38 ,  H01L23/473

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L23/38 ,  H01L23/473 ,  H01L2225/06589

Abstract: Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

公开(公告)号：US20230268410A1

公开(公告)日：2023-08-24

申请号：US17677909

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78696

Abstract: IC devices including vertical TFETs are disclosed. An example IC device includes a substrate, a channel region, a first region, and a second region. One of the first and second regions is a source region and another one is a drain region. The first region includes a first semiconductor material. The second region includes a second semiconductor material that may be different from the first semiconductor material. The first region and the second region are doped with opposite types of dopants. The channel region includes a third semiconductor material that may be different from the first or second semiconductor material. The channel region is between the first region and the second region. The first region is between the channel region and the substrate. In some embodiments, the first or second region is formed through layer transfer or epitaxy (e.g., graphoepitaxy, chemical epitaxy, or a combination of both).

公开(公告)号：US20230268392A1

公开(公告)日：2023-08-24

申请号：US17678928

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0669 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/78618 ,  H01L29/66742 ,  H01L27/0886

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Embodiments of the present disclosure are based on recognition that extending at least one of two S/D contacts of a transistor into a channel layer while keeping it separated from a corresponding gate stack by a channel material may allow keeping the footprint of the transistor relatively small while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower. For multiple transistors, some of the S/D contacts may be shared to further increase transistor density.

公开(公告)号：US20230180483A1

公开(公告)日：2023-06-08

申请号：US17542760

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple hysteretic capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N hysteretic capacitors coupled to the access transistor in a way that allows selecting all of the N hysteretic capacitors for performing READ and/or WRITEs operation when the access transistor is ON. The IC device further includes W wordlines, B bitlines, and P platelines, where N, M, W, B, and P are design variables, each being an integer greater than 1. IC devices implementing memory with one access transistor for multiple hysteretic capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high density embedded memory compatible with advanced CMOS processes.

公开(公告)号：US20230064541A1

公开(公告)日：2023-03-02

申请号：US17462058

申请日：2021-08-31

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Kimin Jun ,  Wilfred Gomes ,  Hui Jae Yoo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.

公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.

公开(公告)号：US20220415811A1

公开(公告)日：2022-12-29

申请号：US17358207

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L27/108 ,  H01L29/786

Abstract: IC devices with backend memory and electrical feedthrough networks of interconnects between the opposite sides of the IC devices, and associated assemblies, packages, and methods, are disclosed. An example IC device includes a back-side interconnect structure, comprising back-side interconnects; a frontend layer, comprising frontend transistors; a backend layer, comprising backend memory cells and backend interconnects; and a front-side interconnect structure, comprising front-side interconnects. In such an IC device, the frontend layer is between the back-side interconnect structure and the backend layer, the backend layer is between the frontend layer and the front-side interconnect structure, and at least one of the back-side interconnects is electrically coupled to at least one of the front-side interconnects by an electrical feedthrough network of two or more of the backend interconnects.

公开(公告)号：US20220392957A1

公开(公告)日：2022-12-08

申请号：US17342144

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Van H. Le ,  Hui Jae Yoo

IPC: H01L27/24 ,  H01L27/22

Abstract: IC devices with stacked backend memory with resistive switching devices are disclosed. An example IC device includes a support structure, a frontend layer with a plurality of frontend devices, and a backend layer with a plurality of resistive switching devices, the resistive switching devices being, e.g., part of memory cells of stacked backend memory. For example, the backend layer may implement stacked arrays of 1T-1RSD memory cells, with resistive switching devices coupled to some S/D regions of access transistors of the memory cells. Such memory cells may be used to implement stacked eMRAM or eRRAM, with access transistors being TFTs. Stacked TFT-based eMRAM or eRRAM as described herein may help increase density of MRAM or RRAM cells, hide the peripheral circuits that control the memory operation below the memory arrays, and address the scaling challenge of some conventional memory technologies.

公开(公告)号：US20220375916A1

公开(公告)日：2022-11-24

申请号：US17323425

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert W. Dewey ,  Jack T. Kavalieros ,  Abhishek A. Sharma ,  Willy Rachmady

IPC: H01L25/18 ,  H01L25/065 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Described herein are IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a compute die, a multilayer memory structure, and an oxide bonding interface coupling the compute die to the multilayer memory structure. The oxide bonding interface includes metal interconnects and an oxide material surrounding the metal interconnects and bonding the compute die to the memory structure.