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11.发明申请公开(公告)号：US20200073810A1
公开(公告)日：2020-03-05
申请号：US16566188
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Andrew T. Lauritzen , Gabor Liktor , Tomer Bar-On , Hugues Labbe , John G. Gierach , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , Balaji Vembu , Altug Koker
IPC: G06F12/0862 , G06F12/0875 , G06F9/30 , G06T1/20 , G06F9/38 , G06F12/0855 , G06F12/0811
Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
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公开(公告)号：US20180293787A1
公开(公告)日：2018-10-11
申请号：US15483409
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Hugues Labbe , Tomer Bar-On , Gabor Liktor , Andrew T. Lauritzen , John G. Gierach
CPC classification number: G06T15/005 , G06T15/30 , G06T15/40
Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
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公开(公告)号：US20240394956A1
公开(公告)日：2024-11-28
申请号：US18675746
申请日：2024-05-28
Applicant: Intel Corporation
Inventor： Sven Woop , Michael J. Doyle , Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Carsten Benthin , Prasoonkumar Surti , Holger Gruen , Stephen Junkins , Adam Lake , Bret G. Alfieri , Gabor Liktor , Joshua Barczak , Won-Jong Lee
Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
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公开(公告)号：US11748302B2
公开(公告)日：2023-09-05
申请号：US17561427
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC: G06F16/13 , G06F9/38 , G06F9/30 , G06F16/11 , G06F16/172 , G06F9/46 , G06F12/1036 , G06F12/1045 , G06F12/0831
CPC classification number: G06F16/13 , G06F9/30 , G06F9/38 , G06F9/3836 , G06F9/461 , G06F16/113 , G06F16/172 , G06F12/0831 , G06F12/1036 , G06F12/1045 , G06F2201/84
Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20220262059A1
公开(公告)日：2022-08-18
申请号：US17591166
申请日：2022-02-02
Applicant: Intel Corporation
Inventor： Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20220222884A1
公开(公告)日：2022-07-14
申请号：US17529938
申请日：2021-11-18
Applicant: Intel Corporation
Inventor： Hugues Labbe , Tomer Bar-On , Gabor Liktor , Andrew T. Lauritzen , John G. Gierach
Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
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公开(公告)号：US11315304B2
公开(公告)日：2022-04-26
申请号：US17003011
申请日：2020-08-26
Applicant: INTEL CORPORATION
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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公开(公告)号：US11315213B2
公开(公告)日：2022-04-26
申请号：US17061296
申请日：2020-10-01
Applicant: Intel Corporation
Inventor： Michael Doyle , Travis Schluessler , Gabor Liktor , Atsuo Kuwahara , Jefferson Amstutz
Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
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公开(公告)号：US20220076480A1
公开(公告)日：2022-03-10
申请号：US17478161
申请日：2021-09-17
Applicant: Intel Corporation
Inventor： Jonathan Kennedy , Gabor Liktor , Jeffery S. Boles , Slawomir Grajewski , Balaji Vembu , Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski
IPC: G06T15/00 , A63F13/355
Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.
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公开(公告)号：US11263800B2
公开(公告)日：2022-03-01
申请号：US16728375
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Karol Szerszen , Prasoonkumar Surti , Gabor Liktor , Karthik Vaidyanathan , Sven Woop
Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
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