-
1.发明授权公开(公告)号：US12125133B2
公开(公告)日：2024-10-22
申请号：US18371614
申请日：2023-09-22
申请人： Intel Corporation
发明人： Gabor Liktor , Karthik Vaidyanathan , Jefferson Amstutz , Atsuo Kuwahara , Michael Doyle , Travis Schluessler
CPC分类号： G06T15/005 , G06T1/60 , G06T15/06 , G06T2210/21
摘要： Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
-
公开(公告)号：US11880928B2
公开(公告)日：2024-01-23
申请号：US17723772
申请日：2022-04-19
申请人： INTEL CORPORATION
发明人： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
CPC分类号： G06T15/06 , G06T1/60 , G06T15/005 , G06T17/005 , G06T2210/21
摘要： Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
-
公开(公告)号：US10762686B2
公开(公告)日：2020-09-01
申请号：US16235906
申请日：2018-12-28
申请人： Intel Corporation
发明人： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
摘要： Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
-
公开(公告)号：US11727528B2
公开(公告)日：2023-08-15
申请号：US17724299
申请日：2022-04-19
申请人： Intel Corporation
CPC分类号： G06T1/20 , G06F9/3877 , G06F9/3891 , G06F9/5077 , G06F16/9027 , G06T15/005 , G06T15/06 , G06T15/10
摘要： An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
-
公开(公告)号：US11995767B2
公开(公告)日：2024-05-28
申请号：US17083123
申请日：2020-10-28
申请人： Intel Corporation
IPC分类号： G06T17/10 , G06T1/20 , G06T3/4007 , G06T9/00 , G06T15/00 , G06T15/06 , G06T15/08 , G06T17/20
CPC分类号： G06T17/10 , G06T1/20 , G06T3/4007 , G06T9/00 , G06T15/06 , G06T15/08 , G06T17/20 , G06T15/005 , G06T2210/12
摘要： Apparatus and method for compression of acceleration structure build data in a ray tracing implementation. For example, one embodiment of an apparatus comprises: traversal hardware logic to traverse rays through a graphics scene comprising a plurality of primitives; and an acceleration data structure processing unit comprising: a bounding box compressor to compress a set of bounding boxes to generate a plurality of bounding box compression blocks, and an index compressor to compress a set of indices to generate a plurality of index compression blocks, and an acceleration data structure builder for constructing acceleration structures based on bounding box compression blocks and index compression blocks.
-
公开(公告)号：US11321910B2
公开(公告)日：2022-05-03
申请号：US16746636
申请日：2020-01-17
申请人： Intel Corporation
摘要： Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.
-
公开(公告)号：US11315304B2
公开(公告)日：2022-04-26
申请号：US17003011
申请日：2020-08-26
申请人： INTEL CORPORATION
发明人： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
摘要： Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
-
公开(公告)号：US11315213B2
公开(公告)日：2022-04-26
申请号：US17061296
申请日：2020-10-01
申请人： Intel Corporation
摘要： An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
-
9.发明授权公开(公告)号：US11769288B2
公开(公告)日：2023-09-26
申请号：US17868618
申请日：2022-07-19
申请人： Intel Corporation
发明人： Gabor Liktor , Karthik Vaidyanathan , Jefferson Amstutz , Atsuo Kuwahara , Michael Doyle , Travis Schluessler
CPC分类号： G06T15/005 , G06T1/60 , G06T15/06 , G06T2210/21
摘要： Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
-
公开(公告)号：US10832371B2
公开(公告)日：2020-11-10
申请号：US16236305
申请日：2018-12-28
申请人： Intel Corporation
摘要： An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.017 秒)
