发明授权
- 专利标题: Apparatus and method for reduced precision bounding volume hierarchy construction
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申请号: US16746636申请日: 2020-01-17
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公开(公告)号: US11321910B2公开(公告)日: 2022-05-03
- 发明人: Michael Doyle , Karthik Vaidyanathan
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Nicholson De Vos Webster & Elliott LLP
- 主分类号: G06T15/10
- IPC分类号: G06T15/10 ; G06T9/00 ; G06T15/06 ; G06T1/60
摘要:
Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.
公开/授权文献
信息查询
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |
G06T15/10 | .图形效果 |