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    Data processing method, network interface card, and server
    11.
    发明授权
    Data processing method, network interface card, and server 有权

    公开(公告)号：US11620227B2

    公开(公告)日：2023-04-04

    申请号：US17464093

    申请日：2021-09-01

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Tianxiang Chen ,  Weibin Lin ,  Xinyu Hou

    IPC: G06F12/00 ,  G06F12/0875 ,  G06F3/06 ,  G06F13/38 ,  H04L49/90

    Abstract: A data processing method comprising: After receiving an ith Peripheral Component Interconnect Express (PCIe) packet, a network interface card stores a jth instruction segment in a jth storage unit that is in a first storage area. When all n instruction segments of a first send queue entry (SQE) are stored in the first storage area, the network interface card obtains the first SQE, an identifier of a queue pair (QP) to which the first SQE belongs, and a location identifier of the first SQE in the QP according to the instructions in n storage units in the first storage area; the network interface card performs data processing based on the identifier of the QP to which the first SQE belongs and the location identifier of the first SQE in the QP.

    Data Switch Chip and Server
    14.
    发明申请
    Data Switch Chip and Server 有权

    公开(公告)号：US20220114132A1

    公开(公告)日：2022-04-14

    申请号：US17561019

    申请日：2021-12-23

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Xinyu Hou ,  Qun Jia ,  Weibin Liin

    IPC: G06F13/42 ,  G06F13/40

    Abstract: An artificial intelligence (AI) switch chip includes a first AI interface, a first network interface, and a controller. The first AI interface is used by the AI switch chip to couple to a first AI chip in a first server. The first network interface is used by the AI switch chip to couple to a second server. The controller receives, through the first AI interface, data from the first AI chip, and then sends the data to the second server through the first network interface. By using the AI switch chip, when a server needs to send data in an AI chip to another server, an AI interface may be used to directly receive the data from the AI chip, and then the data is sent to the other server through one or more network interfaces coupled to the controller.

    Data Processing Method, Network Interface Card, and Server
    15.
    发明申请
    Data Processing Method, Network Interface Card, and Server 有权

    公开(公告)号：US20210397559A1

    公开(公告)日：2021-12-23

    申请号：US17464093

    申请日：2021-09-01

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Tianxiang Chen ,  Weibin Lin ,  Xinyu Hou

    IPC: G06F12/0875 ,  G06F13/38 ,  G06F3/06 ,  H04L12/861

    Abstract: A data processing method comprising: After receiving an ith Peripheral Component Interconnect Express (PCIe) packet, a network interface card stores a jth instruction segment in a jth storage unit that is in a first storage area. When all n instruction segments of a first send queue entry (SQE) are stored in the first storage area, the network interface card obtains the first SQE, an identifier of a queue pair (QP) to which the first SQE belongs, and a location identifier of the first SQE in the QP according to the instructions in n storage units in the first storage area; the network interface card performs data processing based on the identifier of the QP to which the first SQE belongs and the location identifier of the first SQE in the QP.

    Computer subsystem and computer system with composite nodes in an interconnection structure
    16.
    发明授权
    Computer subsystem and computer system with composite nodes in an interconnection structure 有权

    公开(公告)号：US10409766B2

    公开(公告)日：2019-09-10

    申请号：US15845450

    申请日：2017-12-18

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Jiangen Liu ,  Chenghong He ,  Haibin Wang ,  Xinyu Hou

    IPC: G06F9/30 ,  G06F15/80 ,  G06F15/173 ,  G06F15/167 ,  G06F13/42

    Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

    Storage system, method, and apparatus for processing operation request
    17.
    发明授权
    Storage system, method, and apparatus for processing operation request 有权

    公开(公告)号：US10372343B2

    公开(公告)日：2019-08-06

    申请号：US16103871

    申请日：2018-08-14

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

    Inventor： Sheng Chang ,  Xinyu Hou ,  Haitao Guo

    IPC: G06F3/00 ,  G06F3/06 ,  G06F13/38 ,  G06F13/42 ,  G06F12/00

    Abstract: According to a storage system, method, and apparatus for processing an operation request provided by embodiments of the present invention, a controller directly encapsulates a SCSI protocol operation request into an Ethernet operation request packet at the MAC layer instead of using the TCP/IP protocol layer and a disk enclosure decapsulates the Ethernet operation request to obtain the SCSI protocol operation request and sends the SCSI protocol operation request to a target disk, thereby reducing layers of encapsulation, reducing a processing delay of the storage system, and improving performance of the storage system.

    CPU interconnect device
    18.
    发明授权
    CPU interconnect device 有权
    CPU互连设备

    公开(公告)号：US08990460B2

    公开(公告)日：2015-03-24

    申请号：US13707209

    申请日：2012-12-06

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Sheng Chang ,  Rongyu Yang ,  Xinyu Hou

    IPC: G06F13/36 ,  G06F13/40 ,  G06F15/17 ,  G06F13/42

    CPC classification number: G06F13/40 ,  G06F13/4059 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/17 ,  G06F2213/0038 ,  G06F2213/3852

    Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

    Abstract translation: 本公开提供了一种CPU互连设备，CPU互连设备与包括快速路径互连QPI接口和串行解串联SerDes接口的第一CPU连接，快速路径互连QPI接口接收从CPU发送的串行QPI数据， 将接收到的串行QPI数据转换为并行QPI数据，并将并行QPI数据输出到串联解耦SerDes接口; 串行串行SerDes接口将QPI接口输出的并行QPI数据转换为高速串行SerDes数据，然后将高速串行SerDes数据发送到与另一个CPU连接的另一个CPU互连设备。 可以解决CPU之间的可扩展性差，长数据传输延迟以及现有互连系统成本高的缺陷。

    Data Transmission Method, Device and System
    19.
    发明申请
    Data Transmission Method, Device and System 有权
    数据传输方法，设备和系统

    公开(公告)号：US20150026527A1

    公开(公告)日：2015-01-22

    申请号：US14502326

    申请日：2014-09-30

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Xinyu Hou ,  Sheng Chang ,  Rongyu Yang ,  Guang Lu

    IPC: G06F11/07 ,  G06F11/263 ,  H04L1/08

    CPC classification number: H04L1/24 ,  G06F11/076 ,  G06F11/263 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1635 ,  H04L1/18 ,  H04L1/1825 ,  H04L1/1874 ,  H04L1/20 ,  H04L1/203 ,  H04L1/244

    Abstract: A data transmission method, device and system to improve reliability of a data link. When the sender side detects erroneous data, the erroneous data is discarded and a data retransmission request is sent to the sender side to ensure correctness of received data and improve reliability of the data link; and, when the sender side detects the erroneous data and a bit error rate is greater than a preset bit error rate threshold, the data link gets into auto recovery, and data transmission is resumed after the recovery succeeds, thereby avoiding an excessively high bit error rate, preventing an excessively high probability of omitted checks (the higher the bit error rate is, the higher probability of omitted checks is), and further improving reliability of the data link.

    Abstract translation: 一种提高数据链路可靠性的数据传输方法，设备和系统。 当发送方检测到错误数据时，丢弃错误数据，并向发送方发送数据重发请求，以确保接收到的数据的正确性并提高数据链路的可靠性; 并且当发送方检测到错误数据并且误码率大于预设误码率阈值时，数据链路进入自动恢复，并且在恢复成功之后恢复数据传输，从而避免了过高的位错误 速率，防止忽略检查的概率过高（误码率越高，省略检查的概率越高），并进一步提高数据链路的可靠性。

    Method and system for implementing interconnection fault tolerance between CPU
    20.
    发明授权
    Method and system for implementing interconnection fault tolerance between CPU 有权
    实现CPU间互连容错的方法和系统

    公开(公告)号：US08909979B2

    公开(公告)日：2014-12-09

    申请号：US13707188

    申请日：2012-12-06

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Sheng Chang ,  Haibin Wang ,  Jie Zhang ,  Rongyu Yang ,  Xinyu Hou

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/2005 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/1443

    Abstract: A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

    Abstract translation: 用于实现CPU之间的互连容错的系统，第一CPU和第二CPU通过第一CPU互连设备和第二CPU互连设备实现互连。 该系统在第一CPU互连设备的第一SerDes接口和第二CPU互连设备的第二SerDes接口之间添加数据信道，并通过添加的数据信道发送链路连接状态信息和链路控制信号。 系统监视CPU互连系统中任一链路的链路状态，通过添加的数据信道发送链路状态，在确定第一连接链路，第二连接链路和 第三连接链路故障。

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