公开(公告)号：US20230402430A1

公开(公告)日：2023-12-14

申请号：US18239368

申请日：2023-08-29

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US11830855B2

公开(公告)日：2023-11-28

申请号：US17667104

申请日：2022-02-08

Applicant: Google LLC

Inventor： Namhoon Kim ,  Woon-Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

CPC classification number: H01L25/0657 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US20220139876A1

公开(公告)日：2022-05-05

申请号：US17579012

申请日：2022-01-19

Applicant: Google LLC

Inventor： Woon-Seong Kwon ,  Namhoon Kim ,  Teckgyu Kang ,  Ryohei Urata

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.