公开(公告)号：US20180138264A1

公开(公告)日：2018-05-17

申请号：US15793202

申请日：2017-10-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akimasa KINOSHITA

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/063 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor layer of the first conductivity type provided on a front surface of the wide-bandgap semiconductor substrate of the first conductivity type, a base region of a second conductivity type selectively provided in a surface layer of the wide-bandgap semiconductor layer of the first conductivity type, and a trench having a striped planar pattern. The base regions are cyclically provided in a direction parallel to the trench. At the lower portion of the trench, a portion of the base region extends in a direction parallel to the trench and the base regions are connected to each other.

公开(公告)号：US20180097079A1

公开(公告)日：2018-04-05

申请号：US15716919

申请日：2017-09-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Makoto UTSUMI ,  Akimasa KINOSHITA ,  Yasuhiko OONISHI

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/4236 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n−-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.

公开(公告)号：US20180097069A1

公开(公告)日：2018-04-05

申请号：US15722934

申请日：2017-10-02

Applicant: Fuji Electric Co., Ltd.

Inventor： Makoto UTSUMI ,  Akimasa KINOSHITA

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/1608 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7813

Abstract: A gate trench of a MOS gate formed in the front surface of a silicon carbide substrate includes a first portion that includes the bottom surface of the gate trench, a second portion that is connected to the substrate front surface side of the first portion, and a third portion that is connected to the substrate front surface side of the second portion. In the third portion of the gate trench, an n+ source region is exposed along the sidewalls. The width of the third portion of the gate trench is greater than the widths of the first and second portions and of the gate trench. Upper corners of the gate trench smoothly connect the sidewalls to the substrate front surface. The thickness of a gate insulating film smoothly connected along the bottom surface and sidewalls of the gate trench is substantially uniform over the entire inner wall surface of the gate trench.

公开(公告)号：US20170179235A1

公开(公告)日：2017-06-22

申请号：US15345996

申请日：2016-11-08

Applicant: Fuji Electric Co., Ltd.

Inventor： Akimasa KINOSHITA

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/36

CPC classification number: H01L29/1608 ,  H01L21/02529 ,  H01L29/0615 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66325 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7811 ,  H01L29/872

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, and in the substrate an active region where primary current flows and an edge termination area surrounding the active region. The semiconductor device has a first p-type region and a second p-type region in the edge termination area, and the first p-type region includes therein a plurality of third p-type regions, and the second p-type region includes therein a plurality of fourth p-type regions. The widths between the respective plurality of third p-type regions and the widths between the respective plurality of fourth p-type regions become greater further away from the active region.

公开(公告)号：US20230187489A1

公开(公告)日：2023-06-15

申请号：US17978175

申请日：2022-10-31

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akimasa KINOSHITA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L21/04

CPC classification number: H01L29/0623 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/7813 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0465

Abstract: In an edge termination region, p-type regions and p−-type regions configuring a spatial modulation JTE structure are selectively provided at depth positions apart from a front surface of a semiconductor substrate. Respective bottoms of the p-type regions and the p−-type regions are at depth positions deeper from the front surface of the semiconductor substrate than is a bottom of a p-type peripheral region of a peripheral portion of an active region. An outer-side corner of the bottom of the p-type peripheral region is surrounded by an innermost one of the p-type regions and is free from contact with an n−-type drift region of the edge termination region.

公开(公告)号：US20220376054A1

公开(公告)日：2022-11-24

申请号：US17706301

申请日：2022-03-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Shingo HAYASHI ,  Akimasa KINOSHITA

IPC: H01L29/16

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, first electrodes, a second electrode, and a gate pad portion configured by a gate electrode pad and a connecting portion. The second semiconductor layer includes a first region facing the connecting portion and a second region facing a corner portion of the gate electrode pad, and the first and second regions are free of the second semiconductor regions. The oxide film is provided on surfaces of the second semiconductor regions and the first and second regions, and the oxide film and the gate insulating film are made of a same material.

公开(公告)号：US20210296492A1

公开(公告)日：2021-09-23

申请号：US17161867

申请日：2021-01-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akimasa KINOSHITA

IPC: H01L29/78 ,  H01L29/16

Abstract: A semiconductor device includes an active region through which a main current passes during an ON state. In the active region, the semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, first trenches, a second trench, a polycrystalline silicon layer provided in the second trench via one of the gate insulating films, and a silicide layer selectively provided in a surface layer of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicide layer are electrically connected with the gate electrodes.

公开(公告)号：US20210280707A1

公开(公告)日：2021-09-09

申请号：US17159718

申请日：2021-01-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akimasa KINOSHITA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/167 ,  H01L29/16

Abstract: A semiconductor device, including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at a surface thereof, a plurality of gate insulating films in contact with the second semiconductor layer, a plurality of gate electrodes respectively provided on the gate insulating films, a plurality of first electrodes provided on the second semiconductor layer and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate contains boron, a concentration of the boron therein being in a range from 5×1015/cm3 to 5×1016/cm3.

公开(公告)号：US20190198662A1

公开(公告)日：2019-06-27

申请号：US16168948

申请日：2018-10-24

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akimasa KINOSHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4236

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a gate electrode provided via a gate insulating film, an interlayer insulating film, and a barrier metal. At a temperature T (K) and where a guaranteed time of no negative bias temperature instability is L (h), a surface density tTi1 of Ti contained in the barrier metal satisfies: t Ti   1 > 1 1.58 × 10 5  { ln  ( L 1.74 × 10 - 8 ) + Ea 473 × k - Ea kT } where, k is Boltzmann's constant, and Ea is activation energy satisfying 1.0 (eV)

公开(公告)号：US20190131449A1

公开(公告)日：2019-05-02

申请号：US16221272

申请日：2018-12-14

Applicant: Fuji Electric Co., Ltd.

Inventor： Akimasa KINOSHITA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L21/04 ,  H01L29/04

CPC classification number: H01L29/7813 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734

Abstract: A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n+ source region and a p-type base region and reaches an n− drift region. Between adjacent gate trenches, a first p+ region that goes through the p-type base region in the depth direction and reaches the n− drift region is formed at a position separated from the gate trenches. The first p+ region is formed directly beneath a p++ contact region. The width of the first p+ region is less than the width w1 of the gate trench. A second p+ region is formed at the bottom of the gate trench. The first and second p+ regions are silicon carbide epitaxial layers.