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公开(公告)号：US20180143646A1
公开(公告)日：2018-05-24
申请号：US15804992
申请日：2017-11-06
Inventor： Jung Hee SUK , Yi-Gyeong KIM , Chun-Gi LYUH , Young-Deuk JEON , Min-Hyung CHO
Abstract: Provided are an object recognition device, an autonomous driving system including the same, and an object recognition method using the object recognition device. The object recognition device includes an object frame information generation unit, a frame analysis unit, an object priority calculator, a frame complexity calculator, and a mode control unit. The object frame information generation unit generates object frame information based on a mode control signal. The frame analysis unit generates object tracking information based on object frame information. The object priority calculator generates based on object tracking information. The frame complexity calculator generates a frame complexity based on object tracking information. The mode control unit generates a mode control signal for adjusting an object recognition range and a calculation amount of the object frame information generation unit based on the priority information, the frame complexity, and the resource occupation state.
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Patent Agency Ranking
公开(公告)号：US20240195399A1
公开(公告)日：2024-06-13
申请号：US18223101
申请日：2023-07-18
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H03K5/1565 , G06F1/12 , G11C11/4076 , H03K5/131 , H03K5/135 , H03L7/0812 , H03K2005/00058
Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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公开(公告)号：US20220301603A1
公开(公告)日：2022-09-22
申请号：US17565937
申请日：2021-12-30
Inventor： Young-Deuk JEON , Min-Hyung CHO , Young-Su KWON , Jin Ho HAN
Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.
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公开(公告)号：US20210151091A1
公开(公告)日：2021-05-20
申请号：US16997445
申请日：2020-08-19
Inventor： Young-deuk JEON , Seong Min KIM , Jin Kyu KIM , Joo Hyun LEE , Min-Hyung CHO , Jin Ho HAN
IPC: G11C11/4076 , G11C11/4099 , G11C11/4096
Abstract: Disclosed are a device and a method for calibrating a reference voltage. The reference voltage calibrating device includes a data signal communication unit that transmits/receives a data signal, a data strobe signal receiving unit that receives a first data strobe signal and a second data strobe signal, a voltage level of the second data strobe signal being opposite to a voltage level of the first data strobe signal, and a reference voltage generating unit that sets a reference voltage for determining a data value of the data signal, based on the first data strobe signal and the second data strobe signal, and the reference voltage generating unit adjusts the reference voltage based on the first data strobe signal and the second data strobe signal.
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公开(公告)号：US20200226456A1
公开(公告)日：2020-07-16
申请号：US16742808
申请日：2020-01-14
Inventor： Young-deuk JEON , Byung Jo KIM , Ju-Yeob KIM , Jin Kyu KIM , Ki Hyuk PARK , Mi Young LEE , Joo Hyun LEE , Min-Hyung CHO
Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.
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16.发明申请公开(公告)号：US20180146155A1
公开(公告)日：2018-05-24
申请号：US15653358
申请日：2017-07-18
Inventor： Chun-Gi LYUH , Yi-Gyeong KIM , Jung Hee SUK , Young-Deuk JEON , Min-Hyung CHO
CPC classification number: H04N5/4448 , H04N5/05 , H04N5/23238 , H04N19/44
Abstract: The present disclosure relates to a frame grabber, an image processing system, and an image processing method. A frame grabber according to an embodiment of the inventive concept includes a plurality of decoders, a plurality of image controllers, a plurality of memories, a synchronization controller, and a synchronization memory. The plurality of decoders generate a plurality of image data by decoding a plurality of image signals. The plurality of image controllers generate a plurality of pixel data and a plurality of frame information data on the basis of the plurality of image data. The plurality of memories store the plurality of pixel data. The synchronization controller receives the plurality of frame information data, and generates synchronization data on the basis of the plurality of frame information data. The synchronization memory stores the frame information data and the synchronization data.
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