知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.024 seconds)

    HUMAN BODY COMMUNICATION DEVICE AND OPERATING METHOD OF THE SAME
    11.
    发明申请
    HUMAN BODY COMMUNICATION DEVICE AND OPERATING METHOD OF THE SAME 审中-公开

    公开(公告)号：US20200295848A1

    公开(公告)日：2020-09-17

    申请号：US16816109

    申请日：2020-03-11

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Tae Wook KANG ,  Sung Eun KIM ,  Kwang IL OH ,  Hyuk KIM ,  Mi Jeong PARK ,  Hyung-IL PARK ,  Kyung Jin BYUN ,  Jae-Jin LEE ,  In Gi LIM

    IPC: H04B13/00 ,  H04B1/44

    Abstract: Provided are a human body communication device and an operating method of the same. The human body communication device according to an embodiment of the inventive concept includes a first electrode, a second electrode, a transmitting circuit, a receiving circuit, a ground electrode, and a switch. The transmitting circuit generates a first signal in a transmitting mode and transmits the first signal to the first electrode. The receiving circuit receives a second signal from the first electrode in the receiving mode. The receiving circuit includes a differential amplifier that amplifies a difference between a voltage level of a first input terminal depending on the second signal and a voltage level of a second input terminal. The switch electrically connects the second electrode and the ground electrode in the transmitting mode, and electrically connects the second electrode and the second input terminal in the receiving mode.

    LOW POWER SYSTEM ON CHIP
    15.
    发明申请
    LOW POWER SYSTEM ON CHIP 有权

    公开(公告)号：US20220413544A1

    公开(公告)日：2022-12-29

    申请号：US17847636

    申请日：2022-06-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung HAN ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06F1/10 ,  G06F15/78

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

    SPIKING NEURAL NETWORK CIRCUIT
    17.
    发明申请
    SPIKING NEURAL NETWORK CIRCUIT 有权

    公开(公告)号：US20220156556A1

    公开(公告)日：2022-05-19

    申请号：US17446685

    申请日：2021-09-01

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063 ,  H03K19/20

    Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a first synapse zone and a second synapse zone each including one or more synapses, wherein each of the synapses is configured to perform an operation based on the input spike signal and each weight, and a neuron circuit that generates an output spike signal based on operation results of the synapses. The input spike signal is transferred to the first synapse zone and the second synapse zone through a tree structure, and each of branch nodes of the tree structure includes a driving buffer.

    ELECTRONIC CIRCUIT FOR ADJUSTING PHASE OF CLOCK
    19.
    发明申请
    ELECTRONIC CIRCUIT FOR ADJUSTING PHASE OF CLOCK 审中-公开

    公开(公告)号：US20200067516A1

    公开(公告)日：2020-02-27

    申请号：US16542469

    申请日：2019-08-16

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： KWANG IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Mi Jeong PARK ,  Hyung-IL PARK ,  Kyung Jin BYUN ,  Jae-Jin LEE ,  In Gi LIM

    IPC: H03L7/093

    Abstract: The inventive concept includes an oscillating circuit, a phase inverting circuit, and a phase detecting circuit. The oscillating circuit generates a first clock to be used to sample an input signal. The phase inverting circuit outputs a second clock based on the first clock. The phase detecting circuit generates a control signal having a first logic value when a phase difference between a phase of the input signal and a phase of the second clock is less than a reference value for a reference time or more. The phase detecting circuit generates the control signal having a second logic value when the phase difference is equal to or greater than the reference value or when the phase difference is less than the reference value for a time shorter than the reference time. The phase inverting circuit inverts the phase of the second clock when a logic value of the control signal changes from the first logic value to the second logic value or when a logic value of the control signal changes from the second logic value to the first logic value.

    NEUROMORPHIC ARITHMETIC DEVICE
    20.
    发明申请
    NEUROMORPHIC ARITHMETIC DEVICE 审中-公开

    公开(公告)号：US20180232635A1

    公开(公告)日：2018-08-16

    申请号：US15804912

    申请日：2017-11-06

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kwang IL OH ,  Sung Eun KIM ,  Seong Mo PARK ,  Hyung-IL PARK ,  Jae-Jin LEE ,  Joo Hyun LEE

    IPC: G06N3/063 ,  G06F7/68 ,  G06F5/01

    CPC classification number: G06N3/0635 ,  G06F5/01 ,  G06F7/68 ,  H03K19/20

    Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

Patent Agency Ranking