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    Method and apparatus for performing predicate prediction
    12.
    发明授权
    Method and apparatus for performing predicate prediction 有权
    执行谓词预测的方法和装置

    公开(公告)号：US06353883B1

    公开(公告)日：2002-03-05

    申请号：US09224406

    申请日：1998-12-31

    Applicant: Edward T. Grochowski ,  Hans J. Mulder

    Inventor： Edward T. Grochowski ,  Hans J. Mulder

    IPC: G06F9318

    CPC classification number: G06F9/3842 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3844 ,  G06F9/3861

    Abstract: In one method, a predicted predicate value for a predicate is determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.

    Abstract translation: 在一种方法中，确定谓词的预测谓词值。 然后根据预测的谓词值有条件地执行预测指令。 例如，根据本发明的一个实施例，谓词表存储对应于谓词的历史信息。 耦合到表的流水线接收从历史信息计算的预测谓词值。 管道可以使用该预测的谓词值来有条件地执行预测指令。 实际的谓词值从管道返回到谓词表。

    Using a table to track and locate the latest copy of an operand
    13.
    发明授权
    Using a table to track and locate the latest copy of an operand 失效
    使用表来跟踪和定位操作数的最新副本

    公开(公告)号：US6088790A

    公开(公告)日：2000-07-11

    申请号：US994510

    申请日：1997-12-19

    Applicant: Edward T. Grochowski

    Inventor： Edward T. Grochowski

    IPC: G06F9/38

    CPC classification number: G06F9/30141 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3867

    Abstract: The invention, in one embodiment, is a table for tracking operand locations in a processor pipeline. The table includes an entry for each one of a plurality of general purpose registers. Each entry further includes an indication of which port last wrote to the corresponding register; an indication of a pipeline stage containing the instruction that last wrote to the corresponding register; and an indication of whether the operand resides in the pipeline or in a register.

    Abstract translation: 在一个实施例中，本发明是用于跟踪处理器流水线中的操作数位置的表格。 该表包括用于多个通用寄存器中的每一个的条目。 每个条目还包括最后写入相应寄存器的端口的指示; 包含最后写入相应注册表的指令的流水线阶段的指示; 以及操作数是否在流水线或寄存器中的指示。

    Processor with sleep and deep sleep modes
    14.
    发明授权
    Processor with sleep and deep sleep modes 失效
    具有睡眠和深度睡眠模式的处理器

    公开(公告)号：US6021500A

    公开(公告)日：2000-02-01

    申请号：US852174

    申请日：1997-05-07

    Applicant: Tsan-Kuen Wang ,  Samson X. Huang ,  Mustafiz R. Choudhury ,  Edward T. Grochowski

    Inventor： Tsan-Kuen Wang ,  Samson X. Huang ,  Mustafiz R. Choudhury ,  Edward T. Grochowski

    IPC: G06F1/32

    CPC classification number: G06F1/3203

    Abstract: A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.

    Abstract translation: 处理器具有时钟发生器电路，接收外部睡眠信号的睡眠引脚和耦合到时钟发生器电路和睡眠引脚的第一接口电路。 时钟发生器电路响应于外部时钟信号产生核心时钟信号和总线时钟信号。 当外部休眠信号被断言时，当核心时钟信号和总线时钟信号彼此处于第一预定关系时，处理器进入休眠状态。

    Multiported cache and systems
    15.
    发明授权
    Multiported cache and systems 失效
    多频缓存和系统

    公开(公告)号：US5696935A

    公开(公告)日：1997-12-09

    申请号：US914877

    申请日：1992-07-16

    Applicant: Edward T. Grochowski ,  Mustafiz R. Choudhury

    Inventor： Edward T. Grochowski ,  Mustafiz R. Choudhury

    IPC: G06F12/08

    CPC classification number: G06F12/0853 ,  G06F12/0831

    Abstract: A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to snooping and the remaining address ports provide concurrent access to the cache for references to one or more independent addresses respectively issued by one or more pipes. A tag port is provided for each of the address ports to provide concurrent hit/miss status for each address.

    Abstract translation: 缓存存储器具有多个地址端口和相应的多个标签端口，用于与流水线系统中的多个管道一起使用。 其中一个地址端口专用于窥探，其余的地址端口提供对缓存的并发访问，以引用一个或多个分别由一个或多个管道发出的独立地址。 为每个地址端口提供标签端口，以为每个地址提供并发命中/未命中状态。

    Branch prediction and resolution apparatus for a superscalar computer processor
    16.
    发明授权
    Branch prediction and resolution apparatus for a superscalar computer processor 失效
    用于超标量计算机处理器的分支预测和分辨率装置

    公开(公告)号：US5442756A

    公开(公告)日：1995-08-15

    申请号：US922855

    申请日：1992-07-31

    Applicant: Edward T. Grochowski ,  Donald B. Alpert ,  Jack D. Mills ,  Uri C. Weiser

    Inventor： Edward T. Grochowski ,  Donald B. Alpert ,  Jack D. Mills ,  Uri C. Weiser

    IPC: G06F9/318 ,  G06F9/38

    CPC classification number: G06F9/30192 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867

    Abstract: An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.

    Abstract translation: 一种使用预测分支正确的分支预测和验证来提高超标量流水线计算机性能的装置和方法。 预测分支可以在两个不同流水线阶段之一中解决，并且提供了一种用于处理在任一流水线阶段中解决的分支的方法。 提供一种分支验证方法，其验证架构上正确的指令处于解码和执行阶段。 此外，当多时钟指令需要多个时钟解码时，提供两组预取缓冲器以允许分支预测。

    Method and apparatus for dependency checking in a multi-pipelined microprocessor
    17.
    发明授权
    Method and apparatus for dependency checking in a multi-pipelined microprocessor 失效
    在多流水线微处理器中进行依赖检查的方法和装置

    公开(公告)号：US5416913A

    公开(公告)日：1995-05-16

    申请号：US316804

    申请日：1994-10-03

    Applicant: Edward T. Grochowski ,  Donald B. Alpert ,  Ahmad Zaidi

    Inventor： Edward T. Grochowski ,  Donald B. Alpert ,  Ahmad Zaidi

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/40

    CPC classification number: G06F9/3822 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885

    Abstract: In a superscalar processor capable of executing two integer instructions in parallel, an array of comparators is provided to check for all combinations of register dependency between a pair of sequential program instructions. Additional logic is provided to validate the register fields of the instructions. If no impermissible dependencies are detected and all register fields are valid, the instructions are issued and executed in parallel. Otherwise, the instructions are executed sequentially.

    Abstract translation: 在能够并行执行两个整数指令的超标量处理器中，提供比较器阵列以检查一对顺序程序指令之间的寄存器依赖性的所有组合。 提供附加逻辑来验证指令的寄存器字段。 如果没有检测到不允许的依赖关系，并且所有寄存器字段都有效，则并行发出和执行指令。 否则，依次执行指令。

    Mechanism for estimating and controlling di/dt-induced power supply voltage variations
    18.
    发明授权
    Mechanism for estimating and controlling di/dt-induced power supply voltage variations 有权
    用于估计和控制di / dt感应电源电压变化的机制

    公开(公告)号：US07236920B2

    公开(公告)日：2007-06-26

    申请号：US11317948

    申请日：2005-12-23

    Applicant: Edward T. Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David J. Ayers

    Inventor： Edward T. Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David J. Ayers

    IPC: G06F17/50

    CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5036 ,  G06F2217/78 ,  Y02D10/172

    Abstract: A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

    Abstract translation: 公开了一种用于向特定电压范围内的设备供电的系统。 该系统包括功率传递网络，其特征在于响应功能，以向设备传送电力。 当前计算单元存储表示在连续的时钟周期上由设备绘制的当前幅度序列的值，并将其提供给电流到电压计算单元。 电流对电压计算单元根据从响应函数导出的系数对当前幅度进行滤波，以提供器件所看到的电压的估计。 如果估计电压超出规定范围，则调整设备的运行。

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