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公开(公告)号：US20210335946A1
公开(公告)日：2021-10-28
申请号：US16620653
申请日：2019-03-22
Inventor： Wei Song , Liangchen Yan , Ce Zhao , Heekyu Kim , Yuankui Ding , Leilei Cheng , Yingbin Hu , Wei Li , Yang Zhang
Abstract: The present disclosure relates to a pixel structure. The pixel structure may include a base substrate; a first insulating island on a side of the base substrate; a first electrode on a side of the first insulating island opposite front the base substrate; a second electrode on the base substrate and at a peripheral area of the first insulating island; an active layer electrically connected to the first electrode and the second electrode; a second insulating layer on a side of the active layer opposite from the base substrate; a gate electrode on a side of the second insulating layer opposite from the base substrate; and a third insulating layer on a side of the gate electrode opposite from the base substrate.
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公开(公告)号：US10930786B2
公开(公告)日：2021-02-23
申请号：US16554657
申请日：2019-08-29
Inventor： Yuankui Ding , Ce Zhao , Guangcai Yuan , Yingbin Hu , Leilei Cheng , Jun Cheng , Bin Zhou
IPC: H01L29/786 , H01L27/12 , H01L29/66
Abstract: A thin film transistor (TFT), a manufacturing method, an array substrate, a display panel, and a device is disclosed. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.
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公开(公告)号：US10928050B2
公开(公告)日：2021-02-23
申请号：US16413271
申请日：2019-05-15
Inventor： Qinghe Wang , Leilei Cheng
IPC: F21V23/02 , H01L31/0224 , H02S40/34
Abstract: Provided are a light source structure and a light-emitting device. The light source structure includes a power supply unit, a field effect unit and a light-emitting unit, wherein the power supply unit supplies power to the field effect unit and the light-emitting unit; and the field effect unit includes a vibrator unit that receives sound waves from the outside to generate vibration, so that the field effect unit generates a current varying along with the vibration, and supplies the varying current to the light-emitting unit to generate light with variable light intensity.
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公开(公告)号：US20200155717A1
公开(公告)日：2020-05-21
申请号：US16442860
申请日：2019-06-17
Inventor： Guangyao Li , Luke Ding , Leilei Cheng , Yingbin Hu , Jingang Fang , Ning Liu , Qinghe Wang , Dongfang Wang , Liangchen Yan
IPC: A61L2/03 , C01B32/182
Abstract: A sterilization structure, a sterilization board, and a display device are disclosed. The sterilization structure includes an active layer, wherein, one surface of the active layer has an exposed region, and a material of the active layer includes a laser-induced graphene material.
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公开(公告)号：US10522073B2
公开(公告)日：2019-12-31
申请号：US15986083
申请日：2018-05-22
Inventor： Min He , Chun Cao , Leilei Cheng , Yongchao Huang
IPC: G09G3/3208 , H02J7/00 , H02J7/34
Abstract: The present disclosure provides a sensing circuit and a voltage compensation method. With the sensing circuit according to the present disclosure, a capacitance value of a capacitor to be measured on an internal sensing line of a display panel is determined, a compensation voltage for the internal sensing line is determined according to the capacitance value of the capacitor to be measured, and then voltage compensation is performed on the internal sensing line according to the compensation voltage corresponding to the capacitor to be measured.
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Patent Agency Ranking
公开(公告)号：US20190164472A1
公开(公告)日：2019-05-30
申请号：US15986083
申请日：2018-05-22
Inventor： Min He , Chun Cao , Leilei Cheng , Yongchao Huang
IPC: G09G3/3208 , H02J7/00
Abstract: The present disclosure provides a sensing circuit and a voltage compensation method. With the sensing circuit according to the present disclosure, a capacitance value of a capacitor to be measured on an internal sensing line of a display panel is determined, a compensation voltage for the internal sensing line is determined according to the capacitance value of the capacitor to be measured, and then voltage compensation is performed on the internal sensing line according to the compensation voltage corresponding to the capacitor to be measured.
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17.发明申请公开(公告)号：US20180212182A1
公开(公告)日：2018-07-26
申请号：US15567816
申请日：2017-05-19
Inventor： Yongchao Huang , Yuankui Ding , Leilei Cheng , Min He
CPC classification number: H01L51/5203 , H01L51/0045 , H01L51/50 , H01L51/5012 , H01L51/5056 , H01L51/5072 , H01L51/5088 , H01L51/5092
Abstract: A light emitting unit and a manufacturing method thereof, a display panel and an electronic device. The light emitting unit includes a first electrode, a second electrode and a light emitting layer between the first electrode and the second electrode. A material of the light emitting layer 3 includes graphene. The light emitting layer of the light emitting unit can emit light at a single wavelength.
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公开(公告)号：US12133417B2
公开(公告)日：2024-10-29
申请号：US17432462
申请日：2021-02-24
Inventor： Leilei Cheng , Yongchao Huang , Qinghe Wang , Yang Zhang , Bin Zhou
CPC classification number: H10K59/1201 , H10K59/1213 , H10K59/32 , H10K59/82 , H10K59/87 , H10K71/20 , H10K77/10 , G02F1/1306
Abstract: The disclosure relates to the technical field of display, in particular to a displaying substrate, a manufacturing method thereof and a display panel. The displaying substrate comprises a passivation layer (28) and a flat layer (29) covering the passivation layer (28), wherein the flat layer (29) comprises a first flat via hole and a plurality of second flat via holes, the passivation layer (28) comprises a first passivation via hole, and the first flat via hole and the first passivation via hole form a first sleeve hole (31); and the hole depth of the first flat via hole is smaller than that of each second flat via hole, and the hole depth of the first passivation via hole is greater than or equal to the difference between the maximum hole depth of all the second flat via holes and the hole depth of the first flat via hole.
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公开(公告)号：US12062711B2
公开(公告)日：2024-08-13
申请号：US17449607
申请日：2021-09-30
Inventor： Jun Liu , Luke Ding , Jingang Fang , Bin Zhou , Leilei Cheng , Wei Li
IPC: H01L29/66 , H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/475 , H01L21/4757 , H01L21/4763 , H01L27/12 , H01L29/40 , H01L29/417 , H01L29/786
CPC classification number: H01L29/66969 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L21/44 , H01L21/475 , H01L21/47573 , H01L21/47635 , H01L27/1288 , H01L29/401 , H01L29/7869 , H01L29/41733 , H01L29/78633
Abstract: A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.
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公开(公告)号：US11961848B2
公开(公告)日：2024-04-16
申请号：US17265789
申请日：2020-05-14
Inventor： Jun Liu , Liangchen Yan , Bin Zhou , Yadong Liang , Ning Liu , Leilei Cheng , Jingang Fang
IPC: H01L27/12 , H01L21/02 , H01L21/4757 , H01L21/4763
CPC classification number: H01L27/1248 , H01L27/124 , H01L27/127 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/47573 , H01L21/47635 , H01L27/1225
Abstract: Disclosed are a display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a substrate base, and an active layer, a gate insulating layer, a first metal film layer, an interlayer insulating layer, a second metal film layer, and a passivation layer stacked in sequence on the substrate base. The first metal film layer comprises a pattern of a gate and a gate line. The second metal film layer comprises a pattern of a source/drain and a data line. The gate line and the data line are partially arranged opposite to each other. An oxide metal layer is provided on the surface of the side of the region of the gate line opposite to the data line facing the data line.
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