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    Shift register and a driving method thereof, a gate driving circuit and a display device
    11.
    发明授权
    Shift register and a driving method thereof, a gate driving circuit and a display device 有权

    公开(公告)号：US09966957B2

    公开(公告)日：2018-05-08

    申请号：US15519966

    申请日：2016-10-13

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Can Zheng ,  Song Song

    IPC: G11C19/00 ,  H03K19/096 ,  G11C19/28 ,  G09G3/3266

    CPC classification number: H03K19/096 ,  G09G3/3266 ,  G11C19/184 ,  G11C19/28

    Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register includes a control signal generation module, a first low level pulse generation module, a second low level pulse generation module, and a high level pulse generation module. The control signal generation module generates a first control signal and a second control signal. The first low level pulse generation module receives the first control signal and the second control signal and generate a first low level pulse signal. The second low level pulse generation module receives the first control signal and the second control signal and generate a second low level pulse signal. The high level pulse generation module receives the first control signal and generates a high level pulse signal. This shift register reduces the number of circuit elements.

    Shift register unit, driving circuit, display device and driving method
    12.
    发明授权
    Shift register unit, driving circuit, display device and driving method 有权

    公开(公告)号：US12073765B2

    公开(公告)日：2024-08-27

    申请号：US18336565

    申请日：2023-06-16

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Can Zheng

    IPC: G09G3/20

    CPC classification number: G09G3/2092 ,  G09G2310/0286

    Abstract: A shift register unit, a driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit, a first control circuit, and a second control circuit, wherein the first input circuit is electrically connected to a first node; the second input circuit is electrically connected to the first node and a second node; the first control circuit is electrically connected to the second node and a third node; the output circuit is electrically connected to the third node, a second voltage signal line and an output terminal; and the second control circuit is electrically connected to the first node, the third node and a first voltage signal line.

    Shift register, driving method thereof, gate driving circuit and display device
    14.
    发明授权
    Shift register, driving method thereof, gate driving circuit and display device 有权

    公开(公告)号：US11468922B2

    公开(公告)日：2022-10-11

    申请号：US17179699

    申请日：2021-02-19

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Can Zheng

    IPC: G11C7/00 ,  G11C7/10 ,  G09G3/20 ,  G11C7/12 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4074

    Abstract: Shift register includes input sub-circuit coupling input terminal to first node responsive to signal of first clock terminal in input stage, control sub-circuit transmitting signal of second clock terminal to intermediate output terminal according to level at first node and controlling potential of third node according to potential of intermediate output terminal and signal of third clock terminal in input, output and reset stages, pull-up sub-circuit coupling second level terminal to final output terminal responsive to potential of intermediate output terminal in output stage, first voltage stabilization sub-circuit stabilizing voltage between final output terminal and third node responsive to signal of next-stage node connection terminal, pull-down transistor having gate electrode coupled to third node, first electrode coupled to first level terminal, and second electrode coupled to final output terminal. First voltage stabilization sub-circuit lowers potential of third node to level lower than signal of first level terminal in reset stage.

    Shift register and driving method therefor, gate driving circuit and display apparatus
    15.
    发明授权
    Shift register and driving method therefor, gate driving circuit and display apparatus 有权

    公开(公告)号：US10937380B2

    公开(公告)日：2021-03-02

    申请号：US15865550

    申请日：2018-01-09

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Can Zheng

    IPC: G11C19/00 ,  G09G3/36 ,  G09G3/3266 ,  G11C19/28 ,  G09G3/20

    Abstract: Provided is a shift register, comprising an input circuit, an output circuit, and a control circuit, which are electrically connected to a control node. The input circuit is electrically connected with a signal input terminal of the shift register, and is configured to input an input signal provided by the signal input terminal to the control node. The control circuit is electrically connected with a working power supply terminal, and is configured to input an operation voltage provided by the working power supply terminal to the control node. The output circuit is electrically connected with a signal output terminal of the shift register and a clock signal line, and is configured to input one of a voltage of the control node and the first clock signal provided by the clock signal line to the signal output terminal.

    Driving method and device for shift register
    20.
    发明授权
    Driving method and device for shift register 有权

    公开(公告)号：US11854508B2

    公开(公告)日：2023-12-26

    申请号：US17921082

    申请日：2021-05-12

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Guangliang Shang ,  Tian Dong ,  Shuo Huang ,  Can Zheng

    IPC: G09G3/36

    CPC classification number: G09G3/3674 ,  G09G2310/0286

    Abstract: A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.

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