公开(公告)号：US20170177269A1

公开(公告)日：2017-06-22

申请号：US14978001

申请日：2015-12-22

Applicant: ARM Limited

Inventor： Jonathan Curtis Beard

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0683 ,  G06F11/1004 ,  G06F11/1471 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0868

Abstract: Data synchronization between memories of a data processing system is achieved by transferring the data blocks from a first memory to a second memory, forming a hash list from addresses of data blocks that are written to the second memory or modified in the second memory. The hash list may be to identify a set of data blocks that are possibly written to or modified. Data blocks that are possibly modified may be written back from the second memory to the first memory in response to a synchronization event. The hash list may be updated by computing, in hardware or software, hash functions of an address of the transferred or modified data block to determine bit positions to be set. The hash list may be queried by computing hash functions of an address to determine bit positions, and checking bits in the hash list at those bit positions.

公开(公告)号：US10909045B2

公开(公告)日：2021-02-02

申请号：US16228042

申请日：2018-12-20

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Reiley Jeyapaul ,  Roxana Rusitoru

IPC: G06F12/14 ,  G06F12/10

Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.

公开(公告)号：US10884850B2

公开(公告)日：2021-01-05

申请号：US16043975

申请日：2018-07-24

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G06F11/20 ,  G06F12/02 ,  G11C29/00

Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.

公开(公告)号：US10795815B2

公开(公告)日：2020-10-06

申请号：US15166458

申请日：2016-05-27

Applicant: ARM Limited

Inventor： Jonathan Curtis Beard ,  Wendy Elsasser ,  Stephan Diestelhorst

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/08 ,  G06F15/78 ,  G06F9/38

Abstract: A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

公开(公告)号：US20200241839A1

公开(公告)日：2020-07-30

申请号：US16261071

申请日：2019-01-29

Applicant: Arm Limited

Inventor： Kim Richard Schuttenberg ,  Jonathan Curtis Beard ,  Syed Ali Mustafa Zaidi

IPC: G06F5/06 ,  G06F17/50 ,  G06F15/17

Abstract: A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.

公开(公告)号：US10552152B2

公开(公告)日：2020-02-04

申请号：US15166444

申请日：2016-05-27

Applicant: ARM Limited

Inventor： Jonathan Curtis Beard ,  Wendy Elsasser ,  Eric Van Hensbergen ,  Stephan Diestelhorst

IPC: G06F9/30 ,  G06F12/084 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

Abstract: A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

公开(公告)号：US12007905B2

公开(公告)日：2024-06-11

申请号：US17484155

申请日：2021-09-24

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Luis Emilio Pena

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/1072

CPC classification number: G06F12/1063 ,  G06F12/1072 ,  G06F2212/657

Abstract: A hinter data processing apparatus is provided with processing circuitry that determines that an execution context to be executed on a hintee data processing apparatus will require a virtual-to-physical address translation. Hint circuitry transmits a hint to a hintee data processing apparatus to prefetch a virtual-to-physical address translation in respect of an execution context of the further data processing apparatus. A hintee data processing apparatus is also provided with receiving circuitry that receives a hint from a hinter data processing apparatus to prefetch a virtual-to-physical address translation in respect of an execution context of the further data processing apparatus. Processing circuitry determines whether to follow the hint and, in response to determining that the hint is to be followed, causes the virtual-to-physical address translation to be prefetched for the execution context of the data processing apparatus. In both cases, the hint comprises an identifier of the execution context.

公开(公告)号：US11614985B2

公开(公告)日：2023-03-28

申请号：US17130474

申请日：2020-12-22

Applicant: Arm Limited

Inventor： Alexander Donald Charles Chadwick ,  Andrew Brookfield Swaine ,  Gareth James Evans ,  Jonathan Curtis Beard

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/06

Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.

公开(公告)号：US11550585B2

公开(公告)日：2023-01-10

申请号：US17209606

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Roxana Rusitoru ,  Jonathan Curtis Beard ,  Alexander Sebastian Bischoff

IPC: G06F9/34 ,  G06F12/10 ,  G06F9/30

Abstract: A method and apparatus is provided for processing accelerator instructions in a data processing apparatus, where a block of one or more accelerator instructions is executable on a host processor or on an accelerator device. For an instruction executed on the host processor and referencing a first virtual address, the instruction is issued to an instruction queue of the host processor and executed the instruction by the host processor, the executing including translating, by translation hardware of the host processor, the first virtual address to a first physical address. For an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated, by the translation hardware, to a second physical address and the instruction is sent to the accelerator device referencing the second physical address. An accelerator task may be initiated by writing configuration data to an accelerator job queue.

公开(公告)号：US20220308879A1

公开(公告)日：2022-09-29

申请号：US17209606

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Roxana Rusitoru ,  Jonathan Curtis Beard ,  Alexander Sebastian Bischoff

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/10

Abstract: A method and apparatus is provided for processing accelerator instructions in a data processing apparatus, where a block of one or more accelerator instructions is executable on a host processor or on an accelerator device. For an instruction executed on the host processor and referencing a first virtual address, the instruction is issued to an instruction queue of the host processor and executed the instruction by the host processor, the executing including translating, by translation hardware of the host processor, the first virtual address to a first physical address. For an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated, by the translation hardware, to a second physical address and the instruction is sent to the accelerator device referencing the second physical address. An accelerator task may be initiated by writing configuration data to an accelerator job queue.