公开(公告)号：US11841800B2

公开(公告)日：2023-12-12

申请号：US17225614

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Jamshed Jalal ,  Steven Douglas Krueger ,  Klas Magnus Bruce

IPC: G06F12/08 ,  G06F12/0842 ,  G06F12/10 ,  G06F13/40

CPC classification number: G06F12/0842 ,  G06F12/10 ,  G06F13/4027 ,  G06F2212/1024 ,  G06F2212/608

Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request. The stash request handling circuitry is then responsive to the corresponding physical address determined by the address translation circuitry to cause the block of data to be stored at a location within the storage structure associated with the physical address.

公开(公告)号：US11445020B2

公开(公告)日：2022-09-13

申请号：US16828207

申请日：2020-03-24

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Jamshed Jalal ,  Curtis Glenn Dunham ,  Roxana Rusitoru

IPC: G06F11/07 ,  H04L67/1095 ,  G06F11/14 ,  G06F11/30 ,  G06F15/78 ,  G06F12/0808 ,  G06F12/0815

Abstract: Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition and being a request that the copy of the given data item is written to a destination node of the data handling nodes; and the target node is configured, in response to the conditional request: (i) when the outcome of the execution condition is successful, to write the data item to the destination node and to communicate a completion-success indicator to the requesting node; and (ii) when the outcome of the execution condition is a failure, to communicate a completion-failure indicator to the requesting node.

公开(公告)号：US10552212B2

公开(公告)日：2020-02-04

申请号：US15361819

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Roxana Rusitoru

IPC: G06F9/48 ,  G06F9/46

Abstract: Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.

公开(公告)号：US10445094B2

公开(公告)日：2019-10-15

申请号：US15166467

申请日：2016-05-27

Applicant: ARM Limited

Inventor： Jonathan Curtis Beard ,  Wendy Elsasser ,  Shibo Wang

IPC: G06F9/30 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0893 ,  G06F15/78 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0875

Abstract: A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.

公开(公告)号：US10423510B2

公开(公告)日：2019-09-24

申请号：US15724433

申请日：2017-10-04

Applicant: ARM LIMITED

Inventor： Prakash S. Ramrakhyani ,  Jonathan Curtis Beard

IPC: G06F11/30

Abstract: An apparatus comprises a plurality of memory units organized as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.

公开(公告)号：US11934272B2

公开(公告)日：2024-03-19

申请号：US17742875

申请日：2022-05-12

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard ,  Kar-Lik Kasim Wong

IPC: G06F11/14

CPC classification number: G06F11/1407

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

公开(公告)号：US20200371929A1

公开(公告)日：2020-11-26

申请号：US16418380

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Pavel Shamis ,  Eric Ola Harald Liljedahl

IPC: G06F12/0815 ,  G06F12/10 ,  G06F11/30 ,  G06F11/34

Abstract: A method and apparatus for monitoring cache transactions in a cache of a data processing system is provided. Responsive to a cache transaction associated with a transaction address, when a cache controller determines that the cache transaction is selected for monitoring, the cache controller retrieves a pointer stored in a register, determines a location in a log memory from the pointer, and writes a transaction identifier to the determined location in the log memory. The transaction identifier is associated with the transaction address and may be a virtual address, for example. The pointer is updated and stored to the register. The architect of the apparatus may include a mechanism for atomically combining data access instructions with an instruction to commence monitoring.

公开(公告)号：US10671426B2

公开(公告)日：2020-06-02

申请号：US15361770

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Roxana Rusitoru

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F12/0831 ,  G06F13/16 ,  G06F9/52

Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.

公开(公告)号：US10534719B2

公开(公告)日：2020-01-14

申请号：US15819328

申请日：2017-11-21

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Roxana Rusitoru ,  Curtis Glenn Dunham

IPC: G06F12/1009 ,  G06F12/0802 ,  G06F12/06 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1036

Abstract: A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.

公开(公告)号：US20190303143A1

公开(公告)日：2019-10-03

申请号：US15939637

申请日：2018-03-29

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Alejandro Rico Carro

IPC: G06F9/30 ,  G06F15/80

Abstract: A method and apparatus are provided for dynamically determining when an operation, specified by one or more instructions in a data processing system, is suitable for accelerated execution. Data indicators are maintained, for data registers of the system, that indicate when data-flow from a register derives from a restricted source. In addition, instruction predicates are provided for instructions to indicate which instructions are capable of accelerated execution. From the data indicators and the instruction predicates, the microarchitecture of the data processing system determines, dynamically, when the operation is a thread-restricted function and suitable for accelerated execution in a hardware accelerator. The thread-restricted function may be executed on a hardware processor, such as a vector, neuromorphic or other processor.