公开(公告)号：US11409530B2

公开(公告)日：2022-08-09

申请号：US16103995

申请日：2018-08-16

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Pavel Shamis ,  Jamshed Jalal ,  Michael Filippo

IPC: G06F15/00 ,  G06F9/30

Abstract: A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.

公开(公告)号：US11176042B2

公开(公告)日：2021-11-16

申请号：US16418380

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Jonathan Curtis Beard ,  Pavel Shamis ,  Eric Ola Harald Liljedahl

IPC: G06F12/0815 ,  G06F12/10 ,  G06F11/34 ,  G06F11/30

Abstract: A method and apparatus for monitoring cache transactions in a cache of a data processing system is provided. Responsive to a cache transaction associated with a transaction address, when a cache controller determines that the cache transaction is selected for monitoring, the cache controller retrieves a pointer stored in a register, determines a location in a log memory from the pointer, and writes a transaction identifier to the determined location in the log memory. The transaction identifier is associated with the transaction address and may be a virtual address, for example. The pointer is updated and stored to the register. The architect of the apparatus may include a mechanism for atomically combining data access instructions with an instruction to commence monitoring.

公开(公告)号：US11237960B2

公开(公告)日：2022-02-01

申请号：US16418346

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Pavel Shamis

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F12/0804

Abstract: A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.

公开(公告)号：US20200371913A1

公开(公告)日：2020-11-26

申请号：US16418346

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Curtis Glenn Dunham ,  Pavel Shamis

IPC: G06F12/0804

Abstract: A data processing system includes a processor, a memory system, a cache controller and a cache accessible by the processor via the cache controller. The cache controller provides an asynchronous interface between the processor and the memory system. Instructions, issued by the processor to the cache controller, are completed by the cache controller without blocking the processor. In addition, the cache controller tracks a completion status of the memory operation associated with each instruction and enables the completion status to be queried by the processor. Status of the memory operation may be recorded as an entry in a log, where the log, or a property of the log, is accessible by the processor.

公开(公告)号：US20240160452A1

公开(公告)日：2024-05-16

申请号：US18080531

申请日：2022-12-13

Applicant: Arm Limited

Inventor： Eric Van Hensbergen ,  Vasileios Laganakos ,  Pavel Shamis ,  Luis Emilio Pena

IPC: G06F9/445

CPC classification number: G06F9/44521

Abstract: The present disclosure relates generally to systems, devices and/or processes for runtime linking of software component function implementations, and relates more particularly to linking particular function implementations based at least in part on a current execution environment.

公开(公告)号：US20200162549A1

公开(公告)日：2020-05-21

申请号：US16194000

申请日：2018-11-16

Applicant: Arm Limited

Inventor： Pavel Shamis ,  Alejandro Rico Carro

IPC: H04L29/08 ,  G06F16/2455 ,  G06F16/901

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more mobile communication devices and/or processing devices to facilitate and/or support one or more operations and/or techniques for executing distributed memory operations. In particular, some embodiments are directed to techniques for the traversal of vertices of a data structure maintained in a distributed memory system.

公开(公告)号：US11082493B2

公开(公告)日：2021-08-03

申请号：US16194000

申请日：2018-11-16

Applicant: Arm Limited

Inventor： Pavel Shamis ,  Alejandro Rico Carro

IPC: H04L29/08 ,  G06F16/2455 ,  G06F16/901 ,  G06F16/22

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more mobile communication devices and/or processing devices to facilitate and/or support one or more operations and/or techniques for executing distributed memory operations. In particular, some embodiments are directed to techniques for the traversal of vertices of a data structure maintained in a distributed memory system.

公开(公告)号：US10649684B2

公开(公告)日：2020-05-12

申请号：US15460358

申请日：2017-03-16

Applicant: ARM Limited

Inventor： Geoffrey Wyman Blake ,  Pavel Shamis

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/0804 ,  G06F12/0815 ,  G06F13/40 ,  G06F13/42

Abstract: An apparatus has a monitoring data store for storing monitoring data indicating regions of a memory address space to be monitored for changes, which can include at least two non-contiguous regions. Processing circuitry updates the monitoring data in response to an update monitor instruction. Monitoring circuitry monitors accesses to the memory system and provides a notification to the processing circuitry when data associated with one of the monitored regions has changed. This improves performance and energy efficiency by reducing the overhead of polling changes to multiple regions.

公开(公告)号：US20190129871A1

公开(公告)日：2019-05-02

申请号：US15881937

申请日：2018-01-29

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Pavel Shamis ,  Stephan Diestelhorst

IPC: G06F13/16 ,  G06F12/084 ,  G06F12/0871 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1642 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0871 ,  G06F12/0888 ,  G06F13/4086 ,  G06F13/4234 ,  G06F2212/1024 ,  G06F2212/254 ,  G06F2212/284 ,  G06F2212/604 ,  H04L45/745 ,  H04L47/2433 ,  H04L49/10 ,  H04L67/2852

Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.

公开(公告)号：US12001722B2

公开(公告)日：2024-06-04

申请号：US17890456

申请日：2022-08-18

Applicant: Arm Limited

Inventor： Pavel Shamis ,  Honnappa Nagarahalli ,  Jamshed Jalal

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0673

Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.