公开(公告)号：US20230215735A1

公开(公告)日：2023-07-06

申请号：US17986028

申请日：2022-11-14

Applicant: Applied Materials, Inc.

Inventor： Lei LIAO ,  Yung-chen LIN ,  Chi-I LANG ,  Ho-yung David HWANG

IPC: H01L21/311 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32568 ,  H01J37/3211 ,  H01J37/32449 ,  H01J2237/332

Abstract: A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.

公开(公告)号：US20230033038A1

公开(公告)日：2023-02-02

申请号：US17859838

申请日：2022-07-07

Applicant: Applied Materials, Inc.

Inventor： Yung-chen LIN ,  Chi-I LANG ,  Ho-yung HWANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/033

Abstract: Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.

公开(公告)号：US20200335339A1

公开(公告)日：2020-10-22

申请号：US16867095

申请日：2020-05-05

Applicant: Applied Materials, Inc.

Inventor： Tzu-shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KEDLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

IPC: H01L21/033

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

公开(公告)号：US20190181246A1

公开(公告)日：2019-06-13

申请号：US16277634

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Ying ZHANG ,  Qingjun ZHOU ,  Yung-chen LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.