公开(公告)号：US20250157824A1

公开(公告)日：2025-05-15

申请号：US18947949

申请日：2024-11-14

Applicant: Applied Materials, Inc.

Inventor： Shumao ZHANG ,  Qihao ZHU ,  Liqi WU ,  Chih-Hsun HSU ,  Jiang LU ,  Rongjun WANG

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods and processes for selectively depositing a metal fill layer into a feature on the surface of a semiconductor structure. In some embodiments, a method of forming a contact structure includes performing a preclean operation on a contact structure to form a precleaned contact structure. The contact structure includes a silicon-based portion exposed in a cavity of a substrate. The method further includes depositing a metal layer over the precleaned contact structure to form a deposited contact structure. The method further includes introducing a metal halide precursor to the deposited contact structure to at least partially remove the second layer from the deposited contact structure to form an etched contact structure. The method further includes depositing a metal fill layer onto the first layer to form a filled contact structure. The deposited metal fill layer comprises a super conformal profile.

公开(公告)号：US20250054812A1

公开(公告)日：2025-02-13

申请号：US18400819

申请日：2023-12-29

Applicant: Applied Materials, Inc.

Inventor： Qihao ZHU ,  Shumao ZHANG ,  Weifeng YE ,  Yiyang WAN ,  Gary HOW ,  Jianqiu GUO ,  Dong WANG ,  Shihchung CHEN ,  Liqi WU ,  Jiang LU

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.

公开(公告)号：US20240371654A1

公开(公告)日：2024-11-07

申请号：US18142940

申请日：2023-05-03

Applicant: Applied Materials, Inc.

Inventor： Qihao ZHU ,  Chi Hong CHING ,  Liqi WU ,  Tsungjui LIU ,  Gaurav THAREJA ,  Xinke WANG ,  Feng Q. LIU ,  Xi CEN ,  Kai WU ,  Yixiong YANG ,  Yuanhung LIU ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/768

Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.

公开(公告)号：US20240105444A1

公开(公告)日：2024-03-28

申请号：US18139590

申请日：2023-04-26

Applicant: Applied Materials, Inc.

Inventor： Jiang LU ,  Liqi WU ,  Wei DOU ,  Weifeng YE ,  Shih Chung CHEN ,  Rongjun WANG ,  Xianmin TANG ,  Yiyang WAN ,  Shumao ZHANG ,  Jianqiu GUO

IPC: H01L21/02 ,  C23C16/04

CPC classification number: H01L21/0217 ,  C23C16/045 ,  H01L21/02274 ,  H01L21/0228

Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.

公开(公告)号：US20170179252A1

公开(公告)日：2017-06-22

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. TANG ,  Paul F. MA ,  Steven C. H. HUNG ,  Michael CHUDZIK ,  Siddarth KRISHNAN ,  Wenyu ZHANG ,  Seshadri GANGULI ,  Naomi YOSHIDA ,  Lin DONG ,  Yixiong YANG ,  Liqi WU ,  Shih Chung CHEN

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.