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公开(公告)号：US12235703B2
公开(公告)日：2025-02-25
申请号：US18351248
申请日：2023-07-12
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/00 , G06F1/32 , G06F1/3206 , G06F1/3209 , G06F1/324 , G06F1/3287 , G06F1/3296
Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances.
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公开(公告)号：US20210173465A1
公开(公告)日：2021-06-10
申请号：US17177521
申请日：2021-02-17
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/3209 , G06F1/3206 , G06F1/3296 , G06F1/324 , G06F1/3287
Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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公开(公告)号：US11003233B2
公开(公告)日：2021-05-11
申请号：US16379231
申请日：2019-04-09
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Daniel C. Murray , Wei-Han Lien
IPC: G06F1/26 , G06F1/3206 , G06F1/3296 , G06F1/3287 , G06F9/50 , G06F1/324 , G06F1/3203 , G06F1/3228 , G06F1/3215
Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
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公开(公告)号：US10147464B1
公开(公告)日：2018-12-04
申请号：US15628017
申请日：2017-06-20
Applicant: Apple Inc.
Inventor： Shih-Chieh Wen , Jong-Suk Lee , Ramesh B. Gunna
IPC: G06F12/08 , G11C5/14 , G06F1/26 , G06F9/28 , G06F1/30 , G06F11/20 , G06F11/30 , G06F1/00 , G06F9/00
Abstract: An IC in which a power state of a circuit in one power domain is managed based at least in part on a power state of a circuit in another power domain is disclosed. In one embodiment, an IC includes first and second functional circuit blocks in first and second power domains, respectively. A third functional block shared by the first and second is also implemented in the first power domain. A power management unit may control power states of each of the first, second, and third functional circuit blocks. The power management circuit may, when the first functional circuit block is in a sleep state, set a power state of the third functional block in accordance with that of the second functional circuit block.
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公开(公告)号：US20170160791A1
公开(公告)日：2017-06-08
申请号：US15433201
申请日：2017-02-15
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/32
CPC classification number: G06F1/3209 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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Patent Agency Ranking
公开(公告)号：US09411360B2
公开(公告)日：2016-08-09
申请号：US14153296
申请日：2014-01-13
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Wei-Han Lien , Shih-Chieh R. Wen
CPC classification number: G06F1/08 , G06F1/324 , Y02D10/126
Abstract: A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.
Abstract translation: 一种用于管理时钟信号频率变化的系统，包括被配置为输出时钟信号的时钟发生器，耦合到时钟发生器的输出的时钟分配器，被配置为选择时钟信号的频率的处理器，以及 一个时钟管理电路。 时钟管理电路可以被配置为设置时钟发生器以将时钟信号调整到所选择的频率。 时钟管理电路还可以被配置为响应于以所选频率稳定的时钟信号的确定，在多个步骤中调整时钟分频器的除数值。 可以在多个步骤中的每个步骤期间选择新的除数值，并且每个步骤可以在给定时间段之后发生。
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17.发明授权公开(公告)号：US09294103B2
公开(公告)日：2016-03-22
申请号：US14180976
申请日：2014-02-14
Applicant: Apple Inc.
Inventor： Jong-Suk Lee , Shih-Chieh R. Wen , Toshinari Takayanagi , Wei-Han Lien
CPC classification number: H03L7/08 , G06F1/08 , G06F1/3237 , G06F1/324 , H03K5/00006 , H03L7/10 , H03L2207/10 , Y02D10/126 , Y02D10/128 , Y02D50/20
Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.
Abstract translation: 公开了一种在退出低功率状态时实现快速PLL锁定的方法和装置。 在一个实施例中，一种方法包括在PLL锁定到第一频率的第一状态下操作PLL。 该方法还包括对PLL进行编程以在PLL被锁定到第二频率的第二状态下工作。 当PLL处于第一状态时，可能会发生编程，并且编程完成后，PLL可能继续在第一状态下工作。 此后，PLL可以从第一状态转换到低功率状态。 在退出低功率状态时，PLL可以直接转换到第二状态，锁定到第二频率，而不必转换到第一状态或锁定到第一频率。
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公开(公告)号：US09195291B2
公开(公告)日：2015-11-24
申请号：US13924180
申请日：2013-06-21
Applicant: Apple Inc.
Inventor： Jong-Suk Lee
CPC classification number: G06F1/3296 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F9/5083 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22
Abstract: In an embodiment, a digital power estimator (DPE) may be provided that may monitor the processors to estimate the amount of power being consumed. If the estimate exceeds a power threshold, the DPE may throttle one or more of the processors. Additionally, throttling events may be monitored to determine if a change in the operating point is desired. In one embodiment, the DPE throttling events may be counted, and if the counts exceed a count threshold, a change in the operating point to a reduced operation point may be requested. Additionally, if the DPE estimate is below the power threshold (or a second power threshold), a second count of events may be maintained. If the second count exceeds a threshold and the operating point is the reduced operating point, a return to the original operating point may be requested.
Abstract translation: 在一个实施例中，可以提供数字功率估计器（DPE），其可以监视处理器以估计正在消耗的功率的量。 如果估计值超过功率阈值，DPE可以调节一个或多个处理器。 此外，可以监视节流事件以确定是否需要改变工作点。 在一个实施例中，可以对DPE节流事件进行计数，并且如果计数超过计数阈值，则可以请求对减小的操作点的操作点的改变。 另外，如果DPE估计低于功率阈值（或第二功率阈值），则可以维持事件的第二计数。 如果第二计数超过阈值，并且操作点是减小的操作点，则可以请求返回到原始操作点。
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公开(公告)号：US20240045680A1
公开(公告)日：2024-02-08
申请号：US18453010
申请日：2023-08-21
Applicant: Apple Inc.
Inventor： Ran Aharon Chachick , Aditya Kesiraju , Andrew J. Beaumont-Smith , Jong-Suk Lee
CPC classification number: G06F9/30123 , G06F15/80 , G06F9/3877 , G06F9/384 , G06F9/3009
Abstract: A coprocessor with register renaming is disclosed. An apparatus includes a plurality of processors and a coprocessor respectively configured to execute processor instructions and coprocessor instructions. The coprocessor receives coprocessor instructions from ones of the processors. The coprocessor includes an array of processing elements and a result register set comprising storage elements respectively distributed within the array of processing elements. For a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member. The result register set implements a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different processors. Based on a determination that one of the contexts is inactive, the coprocessor is configured to store coprocessor instruction results corresponding to an active context within storage elements of the result register set corresponding to the inactive context.
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公开(公告)号：US20230122955A1
公开(公告)日：2023-04-20
申请号：US17821394
申请日：2022-08-22
Applicant: Apple Inc.
Inventor： John H. Mylius , Conrad H. Ziesler , Daniel C. Murray , Jong-Suk Lee , Rohit Kumar
IPC: G06F1/3209 , G06F1/3296 , G06F1/3206 , G06F1/324 , G06F1/3287
Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
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