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公开(公告)号：US20180351561A1
公开(公告)日：2018-12-06
申请号：US16102445
申请日：2018-08-13
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, JR.
CPC classification number: H03K5/135 , H03L7/081 , H03L7/1976
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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公开(公告)号：US20180241405A1
公开(公告)日：2018-08-23
申请号：US15960523
申请日：2018-04-23
Applicant: Apple Inc.
Inventor： Robert K. Kong , Feng Zhao , Wei Deng
CPC classification number: H03L7/1974 , H03L7/089 , H03L7/0891 , H03L7/099 , H03L7/183 , H03L7/191 , H03L7/1976
Abstract: An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.
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公开(公告)号：US09954542B1
公开(公告)日：2018-04-24
申请号：US15421884
申请日：2017-02-01
Applicant: Apple Inc.
Inventor： Robert K. Kong , Feng Zhao , Wei Deng
CPC classification number: H03L7/1974 , H03L7/089 , H03L7/0891 , H03L7/099 , H03L7/183 , H03L7/191 , H03L7/1976
Abstract: An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.
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Patent Agency Ranking
公开(公告)号：US20180234099A1
公开(公告)日：2018-08-16
申请号：US15429948
申请日：2017-02-10
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, JR.
CPC classification number: H03L7/091 , H03L7/0891 , H03L7/099 , H03L7/1974
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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公开(公告)号：US20150090570A1
公开(公告)日：2015-04-02
申请号：US14501121
申请日：2014-09-30
Applicant: Apple Inc.
Inventor： Hilbert T. Kwan , Jeffrey L. Yen , Craig C. Leong , James J. Niu , Keith J. Hendren , Yanyang Yuan , Feng Zhao , Wanshan Li , Derrick T. Jue , Ze Hong
CPC classification number: H01H13/83 , B05D5/06 , B23K26/38 , G06F3/0202 , H01H3/125 , H01H13/88 , H01H2219/028 , H01H2219/039 , H01H2219/056 , H01H2221/058 , H01H2221/07 , H01H2229/02 , Y10T29/49826
Abstract: An illuminated metal keycap having a legend diffuser material that may diffuse light through a legend opened in a background layer. The background layer may be opaque and the legend may be transparent. The metal keycap is adhered to a scissor mechanism positioned above electrical switch circuitry. Included within, below, or adjacent to the scissor mechanism may be one or more light sources positioned to emit light through the metal keycap, around the perimeter of the metal keycap, and/or through the background layer.
Abstract translation: 具有可以通过在背景层中打开的图例使光漫射的图例扩散器材料的照明的金属键帽。 背景层可以是不透明的，并且图例可以是透明的。 金属键帽粘附在位于电气开关电路上方的剪刀机构上。 包括在剪刀机构内，下面或邻近的剪刀机构可以是一个或多个光源，其被定位成通过金属键帽围绕金属键帽的周边和/或通过背景层发光。
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公开(公告)号：US11469710B2
公开(公告)日：2022-10-11
申请号：US17348414
申请日：2021-06-15
Applicant: Apple Inc.
Inventor： Feng Zhao , Utku Seckin
Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.
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公开(公告)号：US20200350919A1
公开(公告)日：2020-11-05
申请号：US16401737
申请日：2019-05-02
Applicant: Apple Inc.
Inventor： Cristian Marcu , Feng Zhao , Wei Deng , Chunwei Chang , Robert K. Kong , Saeed Chehrazi
Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
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公开(公告)号：US10050634B1
公开(公告)日：2018-08-14
申请号：US15429948
申请日：2017-02-10
Applicant: Apple Inc.
Inventor： Feng Zhao , Wei Deng , Dennis M. Fischette, Jr.
Abstract: A system includes an oscillator, a frequency divider, and a delay circuit. The oscillator may generate a clock signal using a reference signal. A frequency of the clock signal may be a non-integer multiple of a frequency of the reference signal. The frequency divider may generate a feedback signal using the clock signal and an adjustment factor based on the non-integer multiple. The delay circuit may select a particular delayed feedback signal from a plurality of delayed feedback signals based on a value of the adjustment factor. Each of the delayed feedback signals may be generated using periods of the clock signal. The delay circuit may also modify the particular delayed feedback signal using a portion of a period of the clock signal based on the adjustment factor. The oscillator may also adjust the frequency of the clock signal using the reference signal and the particular delayed feedback signal.
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