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    DISTRIBUTED MULTI-DIE PROTOCOL APPLICATION INTERFACE
    11.
    发明申请
    DISTRIBUTED MULTI-DIE PROTOCOL APPLICATION INTERFACE 审中-公开

    公开(公告)号：US20190179792A1

    公开(公告)日：2019-06-13

    申请号：US16208238

    申请日：2018-12-03

    Applicant: Altera Corporation

    Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

    IPC: G06F13/42 ,  G06F5/06 ,  H04L29/06

    Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

    Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder
    12.
    发明授权
    Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder 有权
    在具有FEC编码器的系统的IEEE 1588中实现精确时间戳的方法

    公开(公告)号：US09300421B2

    公开(公告)日：2016-03-29

    申请号：US14058718

    申请日：2013-10-21

    Applicant: Altera Corporation

    Inventor： Haiyun Yang ,  David W. Mendel ,  Keith Duwel ,  Huy Ngo ,  Herman Henry Schmit

    IPC: H04J3/06

    CPC classification number: H04J3/0697 ,  H04J3/0667 ,  H04L1/0042

    Abstract: Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.

    Abstract translation: 公开了用于允许集成电路或设备内的通信系统中的介质访问控制（MAC）层在例如精确时间协议（PTP）协议时准确地确定时间戳点和时间戳值的系统和方法和系统 正在由通信系统使用。 通信系统可以使用精确时间戳点和时间戳值的这种确定来解释并补偿由MAC层发送的数据帧中的前向纠错（FEC）子层改变的时间偏移。 从FEC向MAC提供反馈，以允许MAC将数据帧的时间戳点和时间戳值对齐前导码精确地确定到由FEC子层输出的FEC比特块的开头。

    Scalable interconnect modules with flexible channel bonding
    13.
    发明授权
    Scalable interconnect modules with flexible channel bonding 有权
    可扩展的互连模块，具有灵活的通道结合

    公开(公告)号：US09042404B2

    公开(公告)日：2015-05-26

    申请号：US13925284

    申请日：2013-06-24

    Applicant: ALTERA CORPORATION

    Inventor： Keith Duwel ,  Michael Menghui Zheng ,  Vinson Chan ,  Kalyan Kankipati

    IPC: H04J3/16 ,  H04J3/04 ,  H04L5/22 ,  H04J3/06

    CPC classification number: H04J3/1682 ,  H04J3/04 ,  H04J3/0685 ,  H04L5/22 ,  H04Q2213/13208 ,  H04Q2213/13322

    Abstract: The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

    Abstract translation: 本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。 公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。 根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。 这有利地允许优化用于两种类型的通道结合的配置。 在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。 这种去耦有利地消除了先前架构的刚性约束。

    Multichip package with protocol-configurable data paths
    15.
    发明授权
    Multichip package with protocol-configurable data paths 有权

    公开(公告)号：US12086088B2

    公开(公告)日：2024-09-10

    申请号：US18306100

    申请日：2023-04-24

    Applicant: Altera Corporation

    Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

    IPC: G06F13/40 ,  G06F5/06 ,  G06F13/42

    CPC classification number: G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

    MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS
    16.
    发明公开
    MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS 审中-公开

    公开(公告)号：US20230289309A1

    公开(公告)日：2023-09-14

    申请号：US18306100

    申请日：2023-04-24

    Applicant: Altera Corporation

    Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

    IPC: G06F13/40 ,  G06F13/42 ,  G06F5/06

    CPC classification number: G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

    Distributed multi-die protocol application interface
    17.
    发明授权
    Distributed multi-die protocol application interface 有权

    公开(公告)号：US11169951B2

    公开(公告)日：2021-11-09

    申请号：US17096896

    申请日：2020-11-12

    Applicant: Altera Corporation

    Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

    IPC: G06F13/42 ,  H04L29/06 ,  G06F5/06 ,  H04L12/947

    Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

    Multichip package with protocol-configurable data paths
    18.
    发明授权
    Multichip package with protocol-configurable data paths 有权

    公开(公告)号：US10884964B2

    公开(公告)日：2021-01-05

    申请号：US16436771

    申请日：2019-06-10

    Applicant: Altera Corporation

    Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

    IPC: G06F13/40 ,  G06F5/06 ,  G06F13/42

    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

    Apparatus and methods for communicating with programmable devices
    20.
    发明授权
    Apparatus and methods for communicating with programmable devices 失效
    用于与可编程器件通信的装置和方法

    公开(公告)号：US08719458B2

    公开(公告)日：2014-05-06

    申请号：US14025680

    申请日：2013-09-12

    Applicant: Altera Corporation

    Inventor： Renxin Xia ,  Juju Joyce ,  Nitin Prasad ,  Kerry Veenstra ,  Keith Duwel

    IPC: G06F3/00 ,  G06F13/00

    CPC classification number: G06F13/10 ,  G06F17/5054 ,  H03K19/1776

    Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

    Abstract translation: 电路装置包括可编程逻辑器件。 可编程逻辑器件包括配置逻辑电路。 可编程逻辑器件还包括可配置互连。 电路装置还包括被配置为向可编程逻辑器件提供数据的存储装置。 存储装置经由双向接口与可编程逻辑装置进行通信。

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