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    Self-adjusting clock doubler and integrated circuit clock distribution system using same
    11.
    发明授权
    Self-adjusting clock doubler and integrated circuit clock distribution system using same 有权
    自调整时钟倍增器和集成电路时钟分配系统使用相同

    公开(公告)号：US09319037B2

    公开(公告)日：2016-04-19

    申请号：US14171469

    申请日：2014-02-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arun Sundaresan Iyer ,  Alok Baluni ,  Samuel Naffziger ,  Sriram Sambamurthy

    IPC: H03B19/00 ,  H03K5/13 ,  H03K5/00

    CPC classification number: H03K5/131 ,  H03K2005/00058

    Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

    Abstract translation: 在一种形式中，时钟倍频器包括开关逆变器，专用逻辑电路和控制信号发生电路。 开关逆变器具有用于分别接收第一和第二控制信号的第一和第二控制输入，用于接收时钟输入信号的信号输入和输出。 专用逻辑电路具有用于接收时钟输入信号的第一输入端，耦合到开关逆变器的输出端的第二输入端和用于提供时钟输出信号的输出端。 控制信号产生电路响应于时钟输出信号提供第一和第二控制信号。 时钟倍频器可以用于还包括用于提供输入时钟信号的锁相环的集成电路的时钟分配电路，以及每个具有时钟倍增器之一的多个时钟子域。

    SELF-ADJUSTING CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME
    12.
    发明申请
    SELF-ADJUSTING CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME 有权
    自调整时钟双工器和集成电路时钟分配系统

    公开(公告)号：US20150222277A1

    公开(公告)日：2015-08-06

    申请号：US14171469

    申请日：2014-02-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arun Sundaresan Iyer ,  Alok Baluni ,  Samuel Naffziger ,  Sriram Sambamurthy

    IPC: H03L7/081 ,  H03K5/13

    CPC classification number: H03K5/131 ,  H03K2005/00058

    Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

    Abstract translation: 在一种形式中，时钟倍频器包括开关逆变器，专用逻辑电路和控制信号发生电路。 开关逆变器具有用于分别接收第一和第二控制信号的第一和第二控制输入，用于接收时钟输入信号的信号输入和输出。 专用逻辑电路具有用于接收时钟输入信号的第一输入端，耦合到开关逆变器的输出端的第二输入端和用于提供时钟输出信号的输出端。 控制信号产生电路响应于时钟输出信号提供第一和第二控制信号。 时钟倍频器可以用于还包括用于提供输入时钟信号的锁相环的集成电路的时钟分配电路，以及每个具有时钟倍增器之一的多个时钟子域。

    CONFIGURABLE MULTIPLE-DIE GRAPHICS PROCESSING UNIT
    14.
    发明公开
    CONFIGURABLE MULTIPLE-DIE GRAPHICS PROCESSING UNIT 审中-公开

    公开(公告)号：US20240193844A1

    公开(公告)日：2024-06-13

    申请号：US18077424

    申请日：2022-12-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Mark Fowler ,  Samuel Naffziger ,  Michael Mantor ,  Mark Leather

    IPC: G06T15/00 ,  G06F9/38

    CPC classification number: G06T15/005 ,  G06F9/3802

    Abstract: A graphics processing unit (GPU) of a processing system is partitioned into multiple dies (referred to as GPU chiplets) that are configurable to collectively function and interface with an application as a single GPU in a first mode and as multiple GPUs in a second mode. By dividing the GPU into multiple GPU chiplets, the processing system flexibly and cost-effectively configures an amount of active GPU physical resources based on an operating mode. In addition, a configurable number of GPU chiplets are assembled into a single GPU, such that multiple different GPUs having different numbers of GPU chiplets can be assembled using a small number of tape-outs and a multiple-die GPU can be constructed out of GPU chiplets that implement varying generations of technology.

    FLEXIBILE INTERFACES USING THROUGH-SILICON VIA TECHNOLOGY
    16.
    发明申请
    FLEXIBILE INTERFACES USING THROUGH-SILICON VIA TECHNOLOGY 审中-公开

    公开(公告)号：US20190268086A1

    公开(公告)日：2019-08-29

    申请号：US15903253

    申请日：2018-02-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Wuu ,  Samuel Naffziger ,  Michael K. Ciraula ,  Russell Schreiber

    IPC: H04J99/00 ,  H01L23/48 ,  H01L23/00

    Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

    PERFORMANCE STATE BOOST FOR MULTI-CORE INTEGRATED CIRCUIT
    17.
    发明申请
    PERFORMANCE STATE BOOST FOR MULTI-CORE INTEGRATED CIRCUIT 有权
    多核集成电路的性能状态提升

    公开(公告)号：US20150106642A1

    公开(公告)日：2015-04-16

    申请号：US14053315

    申请日：2013-10-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Samuel Naffziger ,  Baomin Liu ,  Maxat Touzelbaev

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

    Abstract: An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.

    Abstract translation: 集成电路包括多个处理器核和系统管理单元。 多个处理器核心各自以多个性能状态中的一个操作。 系统管理单元耦合到多个处理器核心，用于设置多个处理器核心的性能状态。 系统管理单元基于从估计的功耗计算出的第一温度和基于温度测量的第二温度来提高多个处理器核心的第一处理器核心的第一性能状态。

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