公开(公告)号：US20240324248A1

公开(公告)日：2024-09-26

申请号：US18474179

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： John Wuu ,  Kevin Gillespie ,  Samuel Naffziger ,  Spence Oliver ,  Rajit Seahra ,  Regina T. Schmidt ,  Raja Swaminathan ,  Omar Zia

IPC: H10B80/00 ,  H01L23/544 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L23/544 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/08 ,  H01L2223/54433 ,  H01L2224/06181 ,  H01L2224/08145

Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11822484B2

公开(公告)日：2023-11-21

申请号：US17556257

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  John Wuu ,  Chintan S. Patel

IPC: G06F12/08 ,  G06F12/0895 ,  G06F13/16 ,  G06F12/0891 ,  G06F12/0811

CPC classification number: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/1668

Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

公开(公告)号：US11189540B2

公开(公告)日：2021-11-30

申请号：US16563138

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20230195642A1

公开(公告)日：2023-06-22

申请号：US17556257

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  John Wuu ,  Chintan S. Patel

IPC: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/1668

Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

公开(公告)号：US11676659B2

公开(公告)日：2023-06-13

申请号：US17530815

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  Martin Paul Piorkowski

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/418

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

公开(公告)号：US11205477B2

公开(公告)日：2021-12-21

申请号：US16996024

申请日：2020-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  Martin Paul Piorkowski

IPC: G11C11/419 ,  G11C11/418 ,  G11C7/12

Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.

公开(公告)号：US20190393124A1

公开(公告)日：2019-12-26

申请号：US16563138

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US10509752B2

公开(公告)日：2019-12-17

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G11C5/06 ,  G06F13/38 ,  G06F13/42 ,  H01L25/065 ,  G06F13/40

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

公开(公告)号：US20190332561A1

公开(公告)日：2019-10-31

申请号：US15964647

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Michael K. Ciraula ,  Patrick J. Shyvers

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H01L25/065

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

公开(公告)号：US09355743B2

公开(公告)日：2016-05-31

申请号：US14266039

申请日：2014-04-30

Applicant: Advanced Micro Devices Inc.

Inventor： Amlan Ghosh ,  Keith Allen Kasprak ,  John Wuu ,  John Reginald Riley, III

IPC: G11C29/02 ,  G11C11/419

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5006

Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Abstract translation: 用于静态随机存取存储器（SRAM）阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元，用于存储耦合到多个比特单元的信息，位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。