公开(公告)号：US20210020459A1

公开(公告)日：2021-01-21

申请号：US16513450

申请日：2019-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US20230307405A1

公开(公告)日：2023-09-28

申请号：US17656539

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Lei Fu ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L23/00

CPC classification number: H01L24/24 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/16 ,  H01L24/73 ,  H01L2924/37001 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1427 ,  H01L2924/14252 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/24101 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2224/16137 ,  H01L25/0655

Abstract: An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300° C.

公开(公告)号：US11742301B2

公开(公告)日：2023-08-29

申请号：US16544021

申请日：2019-08-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

公开(公告)号：US11676940B2

公开(公告)日：2023-06-13

申请号：US17003113

申请日：2020-08-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lei Fu ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5381 ,  H01L23/5389 ,  H01L24/13 ,  H01L2225/06541

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

公开(公告)号：US10903168B2

公开(公告)日：2021-01-26

申请号：US16887184

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US20150279773A1

公开(公告)日：2015-10-01

申请号：US14737716

申请日：2015-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Lei Fu ,  Frank Gottfried Kuechenmeister ,  Michael Zhuoying Su

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/073 ,  H01L25/50 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.

Abstract translation: 公开了将堆叠的基板连接到电路板的各种方法和装置。 一方面，提供一种制造方法，其包括将多个基板连接以形成堆叠。 多个基板中的至少一个是半导体芯片。 多个导电通孔形成在多个基板中的第一个中。 多个导电通孔中的每一个包括位于第一基板中的第一端和从第一基板伸出的第二端。