公开(公告)号：US11315883B2

公开(公告)日：2022-04-26

申请号：US16680978

申请日：2019-11-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC: H01L23/544 ,  H01L23/18 ,  H01L23/12

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

公开(公告)号：US10903168B2

公开(公告)日：2021-01-26

申请号：US16887184

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US20250157946A1

公开(公告)日：2025-05-15

申请号：US17957514

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Resham Raj Thapa ,  Xiao Ling Shi ,  Farshad Ghahghahi

IPC: H01L23/00

Abstract: An exemplary stiffener comprises an inner perimeter that substantially surrounds at least one dimension of an integrated circuit coupled to a substrate. The inner perimeter of stiffener comprises a set of boundaries and at least one recess formed into at least one of the boundaries. In addition, the exemplary stiffener also comprises an outer perimeter that extends further outward from the integrated circuit than the inner perimeter. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US20210143104A1

公开(公告)日：2021-05-13

申请号：US16680978

申请日：2019-11-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC: H01L23/544 ,  H01L23/18 ,  H01L23/12

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

公开(公告)号：US11955447B2

公开(公告)日：2024-04-09

申请号：US17528523

申请日：2021-11-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Suming Hu ,  Farshad Ghahghahi

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/11622 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13582 ,  H01L2224/16227 ,  H01L2224/16238

Abstract: In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.

公开(公告)号：US20200294923A1

公开(公告)日：2020-09-17

申请号：US16887184

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.