公开(公告)号：US20190236019A1

公开(公告)日：2019-08-01

申请号：US15884526

申请日：2018-01-31

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Matthew Lucien Evans

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/1036 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/0215 ,  G06F12/1036 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/68

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

公开(公告)号：US11816227B2

公开(公告)日：2023-11-14

申请号：US16624474

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Gareth Rhys Stockwell ,  Jason Parker ,  Djordje Kovacevic ,  Matthew Lucien Evans

IPC: G06F21/60 ,  G06F9/455 ,  G06F9/48 ,  G06F12/14 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/79 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1052

Abstract: An apparatus for processing data comprises memory access circuitry to enforce ownership rights of a plurality of memory regions within a first memory. The memory access circuitry is responsive to a first export command received from a first export command source to perform a first export operation to encrypt the given owned data to form given encrypted data and to store the given encrypted data in a second memory. The memory access circuitry is responsive to a second export command for the given memory region received from a second export command source while the first export operation is being performed to determine whether said second export command source has higher priority than the first export command source and, when the second export command source has a higher priority, to interrupt the first export operation and to perform a second export operation specified by the second export command.

公开(公告)号：US11449437B2

公开(公告)日：2022-09-20

申请号：US16624494

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Djordje Kovacevic

IPC: G06F12/14 ,  G06F21/60 ,  G06F12/1036 ,  G06F9/455

Abstract: An apparatus has processing circuitry for performing data processing in response to software processes and memory access circuitry for enforcing ownership rights for memory regions. A given memory region is associated with an owner realm specified from a multiple realms with each realm corresponding to a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the given memory region (including realms executed at a higher privilege level). The realms are managed according to a realm hierarchy in which each realm other than a root realm is a child realm initialised in response to a command triggered by its parent realm. In response to an invalidation command, a realm management unit makes the target realm and any descendant realm of the target realm inaccessible to the processing circuitry.

公开(公告)号：US11269634B2

公开(公告)日：2022-03-08

申请号：US16531206

申请日：2019-08-05

Applicant: Arm Limited

Inventor： David Hennah Mansell ,  Nigel John Stephens ,  Matthew Lucien Evans

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38

Abstract: A data processing apparatus is provided comprising: a plurality of storage circuits to store data. Execution circuitry performs one or more operations using the storage circuits in response to instructions. The instructions include a relinquish instruction. The execution circuitry responds to the relinquish instruction by indicating that at least one of the plurality of storage circuits is an unused storage circuit and the execution circuitry affects execution of future instructions based on the unused storage circuit after executing the relinquish instruction.

公开(公告)号：US11237957B2

公开(公告)日：2022-02-01

申请号：US16647659

申请日：2018-10-11

Applicant: ARM Limited

Inventor： Jason Parker ,  Djordje Kovacevic ,  Gareth Rhys Stockwell ,  Matthew Lucien Evans

IPC: G06F12/02 ,  G06F12/14

Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.

公开(公告)号：US11113209B2

公开(公告)日：2021-09-07

申请号：US16625924

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans ,  Jason Parker ,  Gareth Rhys Stockwell ,  Martin Weidmann

IPC: G06F12/14 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891 ,  G06F12/1027

Abstract: An apparatus has a translation cache (100) comprising a number of entries for specifying address translation data. Each entry (260) also specifies a translation context identifier (254) associated with the address translation data and a realm identifier (270) identifying one of a number of realms. Each realm corresponds to at least a portion of at least one software process executed by processing circuitry (8). In response to a memory access a lookup of the translation cache (100) is triggered. When the lookup misses in the cache (100), control circuitry (280) prevents allocation of address translation data to the cache when the current realm is excluded from accessing the target memory region by an owner realm specified for the target memory region. In the lookup, whether a given entry (260) matches the memory access depends on both a translation context identifier comparison and a realm identifier comparison.

公开(公告)号：US10423537B2

公开(公告)日：2019-09-24

申请号：US15884526

申请日：2018-01-31

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Matthew Lucien Evans

IPC: G06F12/10 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/1036 ,  G06F12/02

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

公开(公告)号：US10146602B2

公开(公告)日：2018-12-04

申请号：US15054567

申请日：2016-02-26

Applicant: ARM LIMITED

Inventor： Matthew Lucien Evans

IPC: G06F11/07 ,  G06F12/10 ,  G06F9/455 ,  G06F12/109

Abstract: A host data processing system provides a virtual operating environment for a guest data processing system. A transaction is initiated for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system. For a stalled transaction incurring an error, the following are performed: (i) storing identification information relating to that transaction including data identifying the requesting device; (ii) providing translation error condition information to the overseeing guest system; and (iii) deferring handling of the stalled transaction until a subsequent command is received from that guest system. Initiation of a closure process for a guest system initiates cancellation of certain stalled transactions.

公开(公告)号：US08924615B2

公开(公告)日：2014-12-30

申请号：US13661456

申请日：2012-10-26

Applicant: ARM Limited

Inventor： Richard Roy Grisenthwaite ,  Anthony Jebson ,  Andrew Christopher Rose ,  Matthew Lucien Evans

IPC: G06F13/26 ,  G06F13/24

CPC classification number: G06F13/26 ,  G06F13/24

Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Abstract translation: 提供全局中断号码空间38用于消息信号中断。 中断目的地10,12,14,16提供有等待中断高速缓存24，其中由全局挂起状态存储器34提供的后备存储器由全部高速缓存或独立的各个未决状态存储器56共享。中断号码空间可以被划分为具有 可编程映射数据用于指示哪些中断目的地负责哪些区域。 当中断从一个中断目的地迁移到另一个中断时，这种可编程映射数据被更新。 在重新分配过程期间，待处理的中断可以被刷新回到全局挂起状态存储器34，使得该待决中断数据可以被新负责的中断目的地拾取。

公开(公告)号：US20240095183A1

公开(公告)日：2024-03-21

申请号：US18263665

申请日：2022-02-02

Applicant: Arm Limited

Inventor： Carlos Garcia-Tobin ,  Bruce James Mathewson ,  Matthew Lucien Evans ,  Richard Roy Grisenthwaite

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027

Abstract: An apparatus and method are provided for storing a plurality of translation entries in a cache, each translation entry corresponding to one of a plurality of page table entries and defining a translation between a first address and a second address, and encoding control information indicative of an attribute of each page table entry; returning, in response to a lookup querying a first lookup address, a corresponding second address when the first lookup address corresponds to one of the plurality of translation entries stored in the cache; modifying at least some of the control information in response to notification of a modification of the attribute in a page table entry; and retaining in the cache at least one translation entry corresponding to the page table entry for use in a subsequent address lookup querying a corresponding first lookup address in response to the notification of the modification of the attribute in the page table entry.